AD7709

–12–

REV. PrA

January 2001

PRELIMINARY TECHNICAL DATA

Communications Register- ( A1, A0= 0,0):

The Communications Register is an 8-bit write-only register. All communications to the part must start with a write

operation to the Communications Register. The data written to the Communications Register determines whether the

next operation is a read or write operation, the type of read operation and to which register this operation takes place.

For read or write operations, once the subsequent read or write operation to the selected register is complete, the inter-

face returns to where it expects a write operation to the Communications Register. This is the default state of the inter-

face, and on power-up or after a

RESET, the AD7709 is in this default state waiting for a write operation to the

Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock

cycles with DIN high, returns the AD7709 to this default state by resetting the part. Table III outlines the bit designa-

tions for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the

Communications Register. CR7 denotes the first bit of the data stream.

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

WEN(0)

R/

W(0)

STBY(0)

OSCPD (0)

0 (0)

0(0)

A1(0)

A(0)

Table III. Communications Register Bit Designations

Bit

Bit

Location

Mnemonic

Description

CR7

WEN

Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications

Register actually takes place. If a 1 is written to this bit, the part will not clock on to subse-

quent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0

is written to the

WEN bit, the next seven bits will be loaded to the Communications Register.

CR6

R /

W

A zero in this bit location indicates that the next operation will be a write to a specified regis-

ter. A one in this position indicates that the next operation will be a read from the designated

register.

CR5

STBY

Standby bit indication.

Set when its required to put the AD7709 in low power mode.

Clear to power up the AD7709.

CR4

OSCPD

Oscillator Power Down Bit.

If this bit is set, then placing the AD7709 in standby mode will stop the crystal oscillator reduc-

ing the power drawn by these parts to a minimum. The oscillator will require 500ms to begin

oscillating when the ADC is taken out of standby mode.

If this bit is cleared the oscillator is not shut off when the ADC is put into standby mode and

will not require the 500ms start-up time when the ADC is taken out of standby.

CR3

0

This bit must be programmed with a logic 0 for correct operation.

CR2

0

This bit must be programmed with a logic 0 for correct operation.

CR1-CR0

A1-A0

Register Address Bits. These address bits are used to address the AD7709’s registers and are

outlined in table IV.

Table IV. AD7709 Register Selection Table

A1

A0

Register

0

0

Communications register during a write operation.

0

0

Status Register register during a read operation.

0

1

Configuration Register

1

0

Filter register

1

1

ADC Data Register