AD7858/AD7858L

REV. B

–5–

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams for

serial Interface Mode 2. The reading and writing occurs after

conversion in Figure 2, and during conversion in Figure 3. To

attain the maximum sample rate of 100 kHz (AD7858L) or

200 kHz (AD7858), reading and writing must be performed

during conversion as in Figure 3. At least 400 ns acquisition

time must be allowed (the time from the falling edge of BUSY

to the next rising edge of

CONVST) before the next conversion

begins to ensure that the part is settled to the 12-bit level. If the

user does not want to provide the

CONVST signal, the conver-

sion can be initiated in software by writing to the control register.

1.6mA

200 A

TO

OUTPUT

PIN

100pF

+2.1V

Figure 1. Load Circuit for Digital Output Timing

Specifications

THREE-STATE

15

6

16

DB15

DB11

DB0

DB15

DB11

DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

THREE-

STATE

Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

THREE-STATE

15

6

16

DB15

DB11

DB0

DB15

DB11

DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

THREE-

STATE

Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)