AD7858LBR datasheet(18/32 Pages) AD

18 / 32 page

REV. B

–18–

AD7858/AD7858L

PERFORMANCE CURVES

Figure 18 shows a typical FFT plot for the AD7858 at 200 kHz

sample rate and 10 kHz input frequency.

FREQUENCY – kHz

–20

–120

100

–40

–60

–80

–100

AVDD = DVDD = 3.3V

fSAMPLE = 200kHz

fIN = 10kHz

SNR = 72.04dB

THD = –88.43dB

Figure 18. FFT Plot

Figure 19 shows the SNR vs. Frequency for different supplies

and different external references.

INPUT FREQUENCY – kHz

100

AVDD = DVDD WITH 2.5V REFERENCE

UNLESS STATED OTHERWISE

5.0V SUPPLIES, WITH 5V REFERENCE

5.0V SUPPLIES

5.0V SUPPLIES, L VERSION

3.3V SUPPLIES

Figure 19. SNR vs. Frequency

Figure 20 shows the Power Supply Rejection Ratio vs. Fre-

quency for the part. The Power Supply Rejection Ratio is de-

fined as the ratio of the power in adc output at frequency f to

the power of a full-scale sine wave.

PSRR (dB) = 10 log (Pf/Pfs)

Pf = Power at frequency f in adc output, Pfs = power of a

full-scale sine wave. Here a 100 mV peak-to-peak sine wave is

coupled onto the AVDD supply while the digital supply is left

unaltered. Both the 3.3 V and 5.0 V supply performances are

shown.

INPUT FREQUENCY – kHz

–78

–80

–90

100

–82

–84

–86

–88

AVDD = DVDD = 3.3V/5.0V,

100mVp-p SINE WAVE ON AVDD

3.3V

5.0V

Figure 20. PSRR vs. Frequency

POWER-DOWN OPTIONS

The AD7858 provides flexible power management to allow the

user to achieve the best power performance for a given through-

put rate. The power management options are selected by

programming the power management bits, PMGT1 and PMGT0,

in the control register and by use of the

SLEEP pin. Table VI

summarizes the power-down options that are available and how

they can be selected by using either software, hardware, or a

combination of both. The AD7858 can be fully or partially

powered down. When fully powered down, all the on-chip cir-

cuitry is powered down and IDD is 1

µA typ. If a partial power-

down is selected, then all the on-chip circuitry except the reference

is powered down and IDD is 400

µA typ. The choice of full or par-

tial power-down does not give any significant improvement in

throughput with a power-down between conversions. This is

discussed in the next section–Power-Up Times. However, a

partial power-down does allow the on-chip reference to be used

externally even though the rest of the AD7858 circuitry is pow-

ered down. It also allows the AD7858 to be powered up faster

after a long power-down period when using the on-chip refer-

ence (See Power-Up Times–Using On-Chip Reference).

When using the

SLEEP pin, the power management bits PMGT1

and PMGT0 should be set to zero (default status on power-up).

Bringing the

SLEEP pin logic high ensures normal operation,

and the part does not power down at any stage. This may be

necessary if the part is being used at high throughput rates when

it is not possible to power down between conversions. If the user

wishes to power down between conversions at lower throughput

rates (i.e. <100 kSPS for the AD7858) to achieve better power

performances, then the

SLEEP pin should be tied logic low.

If the power-down options are to be selected in software only,

then the

SLEEP pin should be tied logic high. By setting the

power management bits PMGT1 and PMGT0 as shown in

Table VI, a Full Power-Down, Full Power-Up, Full Power-

Down Between Conversions, and a Partial Power-Down Be-

tween Conversions can be selected.

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