REV. B

–12–

AD7858/AD7858L

MSB

ZERO

BUSY

SGL/

DIFF

CH2

CH1

CH0

PMGT1

PMGT0

RDSLT1

RDSLT0

2/

3 MODE

X

CALMD

CALSLT1

CALSLT0

STCAL

LSB

STATUS REGISTER BIT FUNCTION DESCRIPTION

Bit

Mnemonic

Comment

15

ZERO

This bit is always 0.

14

BUSY

Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion

or calibration in progress. When this bit is 0, there is no conversion or calibration in progress.

13

SGL/

DIFF

These four bits indicate the channel selected for conversion (see Table III).

12

CH2

11

CH1

10

CH0

9

PMGT1

Power management bits. These bits along with the

SLEEP pin will indicate if the part is in a

8

PMGT0

power-down mode or not. See Table VI for description.

7

RDSLT1

Both of these bits are always 1, indicating it is the status register being read (see Table II).

6

RDSLT0

52/

3 MODE

Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at

1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.

4X

Don’t care bit.

3

CALMD

Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit

indicates a system calibration is selected (see Table IV).

2

CALSLT1

Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a

1

CALSLT0

calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and

0

STCAL

CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing

(see section on the Calibration Registers for more details).

STATUS REGISTER

The arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The

status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits

in the status register are described below. The power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT1 = 1

READ STATUS REGISTER

Figure 6. Flowchart for Reading the Status Register