AD8343 datasheet(13/27 Pages) AD

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REV. 0

AD8343

–13–

DC INTERFACES

Biasing and Decoupling (VPOS, DCPL)

VPOS is the power supply connection for the internal bias cir-

cuit and the LO driver. This pin should be closely bypassed to

GND with a capacitor in the range of 0.01

µF to 0.1 µF. The

DCPL pin provides access to an internal bias node for noise

bypassing purposes. This node should be bypassed to COMM

with 0.1

µF.

Power-Down Interface (PWDN)

The AD8343 is active when the PWDN pin is held low; other-

wise the device enters a low-power state as shown in Figure 3.

PWDN SWEPT

FROM BOTH

3V TO 5V

AND

5V TO 3V

PWDN VOLTAGE – Volts

3.0

3.5

4.0

4.5

5.0

Figure 3. Bias Current vs. PWDN Voltage

To assure full power-down, the PWDN voltage should be within

0.5 V of the supply voltage at VPOS. Normal operation requires

that the PWDN pin be taken at least 1.5 V below the supply

voltage. The PWDN pin sources about 100

µA when pulled to

GND (refer to Pin Function Descriptions). It is not advisable to

leave the pin floating when the device is to be disabled; a resis-

tive pull-up to VPOS is the minimum suggestion.

The AD8343 requires about 2.5

µs to turn OFF when PWDN is

asserted; turn ON time is about 500 ns. Figures 4 and 5 show

typical characteristics (they will vary with bypass component

values). Figure 6 shows the test configuration used to acquire

these waveforms.

200nV

1.00V

CH2

500ns CH2

4.48V

CH1

Figure 4. PWDN Response Time Device ON to OFF

200nV

1.00V

CH2

100ns CH2

4.48V

CH1

Figure 5. PWDN Response Time Device OFF to ON

1nH

0.1 F

VPOS

0.1 F

COMM

AD8343

INPP

INPM

DCPL

VPOS

PWDN

COMM

OUTP

OUTM

COMM

LOIP

LOIM

COMM

MATCHING

NETWORK AND

TRANSFORMER

HP8130

PULSE

GENERATOR

HP8648C

SIGNAL

GENERATOR

TEKTRONIX

TDS694C

OSCILLOSCOPE

RF INPUT

1740MHz

IF OUTPUT

170MHz

LO INPUT

1570MHz

MATCHING

NETWORK AND

TRANSFORMER

HP8648C

SIGNAL

GENERATOR

TRIGGER

Figure 6. PWDN Response Time Test Schematic

AC INTERFACES

Because of the AD8343’s wideband design, there are several

points to consider in its ac implementation; the Basic AC

Signal Connection diagram shown in Figure 7 summarizes

these points. The input signal undergoes a single-ended-to-

differential conversion and is then reactively matched to the

impedance presented by the emitters of the core. The matching

network also provides bias currents to these emitters. Similarly,

the LO input undergoes a single-ended-to-differential transfor-

mation before it is applied to the 50

Ω differential LO port. The

differential output signal currents appear at high-impedance

collectors and may be reactively matched and converted to a

single-ended signal.

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