AD8400 datasheet(13/20 Pages) AD

13 / 20 page

AD8400/AD8402/AD8403

REV. B

–13–

where Dx is the data contained in the 8-bit RDAC# latch, and

RBA is the nominal end-to-end resistance. For example, when

VA = 0 V and B terminal is open circuit, the following output

resistance values will be set for the following RDAC latch codes

(applies to 10 k

Ω potentiometers):

DRWA

(Dec)

(

Ω)

Output State

255

Full Scale

128

5050

Midscale (RS = 0 Condition)

10011

1 LSB

10050

Zero Scale

The typical distribution of RBA from channel-to-channel matches

within

±1%. However, device-to-device matching is process lot

dependent having a

±20% variation. The change in R

BA with

temperature has a positive 500 ppm/

°C temperature coefficient.

The wiper-to-end-terminal resistance temperature coefficient

has the best performance over the 10% to 100% of adjustment

range where the internal wiper contact switches do not contribute

any significant temperature related errors. The graph in Figure

11 shows the performance of RWB tempco vs. code, using the

trimmer with codes below 32 results in the larger temperature

coefficients plotted.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates an output voltage

proportional to the input voltage applied to a given terminal.

For example, connecting A terminal to +5 V and B terminal to

ground produces an output voltage at the wiper starting at zero

volts up to 1 LSB less than +5 V. Each LSB of voltage is equal

to the voltage applied across terminal AB divided by the 256

position resolution of the potentiometer divider. The general

equation defining the output voltage with respect to ground for

any given input voltage applied to terminals AB is:

VW (Dx) = Dx/256

× V

AB + VB

Equation 4

Operation of the digital potentiometer in the divider mode re-

sults in more accurate operation over temperature. Here the

output voltage is dependent on the ratio of the internal resistors,

not the absolute value; therefore, the temperature drift improves

to 15 ppm/

°C.

At the lower wiper position settings, the potentiometer divider

temperature coefficient increases due to the contributions of the

CMOS switch wiper resistance becoming an appreciable portion

of the total resistance from terminal B to the wiper. See Figure 10

for a plot of potentiometer tempco performance versus code

setting.

DIGITAL INTERFACING

The AD8400/AD8402/AD8403 contains a standard SPI com-

patible three-wire serial input control interface. The three inputs

are clock (CLK), CS and serial data input (SDI). The positive-

edge sensitive CLK input requires clean transitions to avoid

clocking incorrect data into the serial input register. For best re-

sults use logic transitions faster than 1 V/

µs. Standard logic

families work well. If mechanical switches are used for product

evaluation, they should be debounced by a flip-flop or other

suitable means. The Figure 38 block diagrams show more detail

of the internal digital circuitry. When CS is taken active low, the

clock loads data into the 10-bit serial register on each positive

clock edge (see Table II).

DAC

LAT

GND

AD8400

CLK

ADDR

DEC

SDI

SER

REG

10-BIT

DAC

LAT

AGND

AD8402

CLK

DAC

LAT

ADDR

DEC

SDI

10-BIT

SER

REG

SHDN

DGND

DAC

LAT

AGND

VDD

AD8403

CLK

SDO

DAC

LAT

ADDR

DEC

SDI

SER

REG

SHDN

DGND

Figure 38. Block Diagrams

AD8400 Datasheet(PDF) 13 Page - Analog Devices

AD8400 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL