AD8401

–8–

REV. 0

An active low pulse, at any time, on the RESET pin asynchro-

nously forces all DAC register bits to zero. The DAC output

voltage becomes zero volts and stays at that value until a new

data word is loaded into the DAC register with a new WR com-

mand. The equivalent input logic for the DAC register loading

is shown in Figure 9.

RESET

CS

WR

DAC REGISTER

D0

D7

INPUT DATA

TO DAC LADDER

Figure 9. Equivalent DAC Register Control Logic

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

–0.1

256

–0.5

0

0

0.5

192

128

64

DIGITAL INPUT CODE – DECIMAL

Figure 10. ADC Linearity Error vs. Digital Code

1.0

–0.1

256

–0.5

0

0

0.5

192

128

64

DIGITAL INPUT CODE – DECIMAL

Figure 11. DAC Linearity Error vs. Digital Code

120

0

4.5

30

10

–3.5

20

–4.5

60

40

50

70

80

90

110

100

3.5

2.5

1.5

0.5

–0.5

–1.5

–2.5

FULL SCALE ERROR – LSB

SS = 300 UNITS

Figure 12. ADC Full-Scale Error Histogram

2.5

–3.0

–1.5

–2.5

–2.0

0

–1.0

–0.5

0.5

1.0

1.5

2.0

100

–25

–50

75

50

25

0

TEMPERATURE –

°C

Figure 13. ADC Full-Scale Error vs. Temperature