AD872ASE datasheet(13/20 Pages) AD

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REV. A

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AD872A

condition or an out-of-range low condition. Note that if the in-

put is driven beyond +1.5 V, the digital outputs may not stay at

+FS, but may actually fold back to midscale.

The AD872A’s CMOS digital output drivers are sized to pro-

vide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause glitches on

the supplies and may affect S/(N+D) performance. Applications

requiring the AD872A to drive large capacitive loads or large

fanout may require additional decoupling capacitors on DRVDD

and DVDD. In extreme cases, external buffers or latches could

be used.

THREE-STATE OUTPUTS

The 44-terminal surface mount AD872A offers three-state out-

puts. The digital outputs can be placed into a three-state mode

by pulling the OUTPUT ENABLE (OEN) pin LOW. Note that

this function is not intended to be used to pull the AD872A on

and off a bus at 10 MHz. Rather, it is intended to allow the ADC

to be pulled off the bus for evaluation or test modes. Also, to

avoid corruption of the sampled analog signal during conversion

(3 clock cycles), it is highly recommended that the AD872A be

placed on the bus prior to the first sampling.

DATA

OUTPUT

ACTIVE

THREE-STATE

OEN

Figure 25. Three-State Output Timing Diagram

For timing budgetary purposes, the typical access and float de-

lay times for the AD872A are 50 ns.

CLOCK INPUT

The AD872A internal timing control uses the two edges of the

clock input to generate a variety of internal timing signals. The

optimal clock input should have a 50% duty cycle; however,

sensitivity to duty cycle is significantly reduced for clock rates of

less than 10 megasamples per second.

20MHz

74XX74

CLK

+5V

Figure 26. Divide-by-Two Clock Circuit

Due to the nature of on-chip compensation circuitry, the duty

cycle should be maintained between 40% and 60% even for

clock rates less than 10 MSPS. One way to realize a 50% duty

cycle clock is to divide down a clock of higher frequency, as

shown in Figure 26.

In this case, a 20 MHz clock is divided by 2 to produce the

10 MHz clock input for the AD872A. In this configuration, the

duty cycle of the 20 MHz clock is irrelevant.

The input circuitry for the CLKIN pin is designed to accom-

modate both TTL and CMOS inputs. The quality of the logic

input, particularly the rising edge, is critical in realizing the best

possible jitter performance for the part: the faster the rising

edge, the better the jitter performance.

As a result, careful selection of the logic family for the clock

driver, as well as the fanout and capacitive load on the clock

line, is important. Jitter-induced errors become more pro-

nounced at higher frequency, large amplitude inputs, where the

input slew rate is greatest.

The AD872A is designed to support a sampling rate of 10

MSPS; running at slightly faster clock rates may be possible,

although at reduced performance levels. Conversely, some slight

performance improvements might be realized by clocking the

AD872A at slower clock rates. Figure 27 presents the S/(N+D)

vs. clock frequency for a 1 MHz analog input.

FREQUENCY – MHz

Figure 27. Typical S/(N+D) vs. Clock Frequency,

fIN = 1 MHz, Full-Scale Input

The power dissipated by the correction logic and output buffers

is largely proportional to the clock frequency; running at re-

duced clock rates provides a slight reduction in power consump-

tion. Figure 28 illustrates this tradeoff.

FREQUENCY – MHz

1.09

1.08

1.07

1.06

1.05

1.04

Figure 28. Typical Power Dissipation vs. Clock Frequency

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