AD9244 datasheet(7/36 Pages) AD

7 / 36 page

REV. A

AD9244

–7–

PIN CONFIGURATION

AGND

AVDD

AGND

CLK–

CLK+

NIC

OEB

D0 (LSB)

D11

D12

D13 (MSB)

OTR

DRVDD

DGND

AVDD

AGND

AVDD

DFS

SENSE

AD9244

TOP VIEW

(NOT TO SCALE)

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

1, 2, 5, 32, 33

AGND

Analog Ground.

3, 4, 31, 34

AVDD

Analog Supply Voltage.

6, 7

CLK–, CLK+

Differential Clock Inputs.

8, 44

NIC

No Internal Connection.

OEB

Digital Output Enable (Active Low).

D0 (LSB)

Least Significant Bit, Digital Output.

11–13, 16–21,

D1–D3, D4–D9,

Digital Outputs.

24–26

D10–D12

14, 22, 30

DGND

Digital Ground.

15, 23, 29

DRVDD

Digital Supply Voltage.

D13 (MSB)

Most Significant Bit, Digital Output.

OTR

Out-of-Range Indicator (Logic 1 indicates OTR).

DFS

Data Format Select. Connect to AGND for straight binary, AVDD for twos complement.

SENSE

Internal Reference Control.

VREF

Internal Reference.

REFGND

Reference Ground.

39–42

REFB, REFT

Internal Reference Decoupling.

DCS

50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND

for external control of both clock edges.

CML

Common-Mode Reference (0.5

× AVDD).

46, 47

VIN+, VIN–

Differential Analog Inputs.

Internal Bias Decoupling.

AD9244 Datasheet(PDF) 7 Page - Analog Devices

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