AD9260EB datasheet(24/36 Pages) AD

24 / 36 page

AD9260

–24–

REV. B

The outputs of each op amp are ac coupled via a small series

resistor and capacitor (i.e., 50

Ω and 0.1 µF) to the respective

inputs of the AD9260. Similar to the dc coupled driver, further

out-of-band noise reduction can be realized with the addition of

100 pF single-ended and differential capacitors, CS and CD.

The lower-cutoff frequency of this ac coupled circuit is deter-

mined by RC and CC in which RC is tied to the common-mode

level pin, CML, of the AD9260 for proper biasing of the inputs.

Although the OPA642 was found to provide the lowest overall

noise and distortion performance (i.e., 88.8 dB and 96 dB

THD @ 100 kHz), the AD8055 (or dual AD8056) suffered

only a 0.5 dB to 1.5 dB degradation in overall performance. It

is worth noting that given the high-level of performance attainable

by the AD9260, special consideration must be given to both the

quality of the test equipment and test setup in its evaluation.

Common-Mode Level

The CML pin is an internal analog bias point used internally by

the AD9260. This pin must be decoupled to analog ground

with at least a 0.1

µF capacitor as shown in Figure 59. The dc

level of CML is approximately AVDD/2.5. This voltage should

be buffered if it is to be used for any external biasing.

Note: the common-mode voltage of the input signal applied to

the AD9260 need not be at the exact same level as CML. While

this level is recommended for optimal performance, the AD9260 is

tolerant of a range of input common-mode voltages around

AVDD/2.5.

CML

AD9260

0.1 F

Figure 59. CML Decoupling

REFERENCE OPERATION

The AD9260 contains an onboard bandgap reference and inter-

nal reference buffer amplifier. The onboard reference provides a

pin-strappable option to generate either a 1 V or 2.5 V output.

With the addition of two external resistors, the user can generate

reference voltages other than 1 V and 2.5 V. Another alterna-

tive is to use an external reference for designs requiring en-

hanced accuracy and/or drift performance. See Table IV for a

summary of the pin-strapping options for the AD9260 reference

configurations. Note, the optimum noise and distortion can only be

achieved with a 2.5 V reference.

Figure 60 shows a simplified model of the internal voltage refer-

ence of the AD9260. A pin-strappable reference amplifier

buffers a 1 V fixed reference. The output from the reference

amplifier, A1, appears on the VREF pin and MUST be de-

coupled with 0.1

µF and 10 µF capacitor to REFCOM. The

voltage on the VREF pin determines the full-scale input span of

the A/D. This input span equals:

Full-Scale Input Span = 1.6

× VREF

The voltage appearing at the VREF pin, as well as the state of

the internal reference amplifier, A1, are determined by the volt-

age appearing at the SENSE pin. The logic circuitry contains

two comparators that monitor the voltage at the SENSE pin.

The comparator with the lowest set point (approximately 0.3 V)

controls the position of the switch within the feedback path of

A1. If the SENSE pin is tied to REFCOM, the switch is con-

nected to the internal resistor network, thus providing a VREF

of 2.5 V. If the SENSE pin is tied to the VREF pin via a short

or resistor, the switch is connected to the SENSE pin. A short

will provide a VREF of 1.0 V while an external resistor network

will provide an alternative VREF SPAN between 1.0 V and

2.5 V. The external resistor network may, for example, be

implemented as a resistor divider circuit. This divider circuit

could consist of a resistor (R1) connected between VREF and

SENSE and another resistor (R2) connected between SENSE

and REFCOM. The other comparator controls internal cir-

cuitry that will disable the reference amplifier if the SENSE pin

is tied to AVDD. Disabling the reference amplifier allows the

VREF pin to be driven by an external voltage reference.

The reference buffer circuit, level shifts the reference to an

appropriate common-mode voltage for use by the internal cir-

cuitry. The on-chip buffer provides the low impedance neces-

sary for driving the internal switched capacitor circuits and

eliminates the need for an external buffer op amp.

The actual reference voltages used by the internal circuitry of

the AD9260 appear on the CAPT and CAPB pins. If VREF is

configured for 2.5 V, thus providing a 4 V full-scale input span,

the voltages appear at CAPT and CAPB are 3.0 V and 1.0 V

respectively. For proper operation when using the internal or an

external reference, it is necessary to add a capacitor network to

decouple the CAPT and CAPB pins. Figure 61 shows the rec-

ommended decoupling network. This capacitive network per-

forms the following three functions: (1) along with the reference

amplifier, A2, it provides a low source impedance over a large

frequency range to drive the A/D internal circuitry, (2) it pro-

vides the necessary compensation for A2, and (3) it bandlimits

the noise contribution from the reference. The turn-on time of

the reference voltage appearing between CAPT and CAPB is

approximately 15 ms and should be evaluated in any power-

down mode of operation.

LOGIC

– +

AD9260

DISABLE

TO A/D

6.25k

DISABLE

7.5k

CAPT

CAPB

VREF

SENSE

REFCOM

Figure 60. Simplified Reference

AD9260EB Datasheet(PDF) 24 Page - Analog Devices

AD9260EB Datasheet(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL