AD9260EB datasheet(31/36 Pages) AD

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AD9260

–31–

REV. B

For two-tone input signals: The user would leave jumpers (JP8)

connected and use IN-1 and IN-2 (J7 and J6) as the connec-

tors for the input signals.

For signal tone input signal: The user would remove jumper

(JP8) and use only IN-1 as the input signal connector.

• Selectable Input Signal Common-Mode Level Source:

The input signal’s common-mode level (CML) can be set by

U10.

To use the Input CML generated by U10: Disconnect jumper

JP13 and Connect resistors RX3 and RX4. The CML gener-

ated by U10 is variable and adjustable using the 1 k

Ω

trimpot R35.

SHIPMENT CONFIGURATION AND QUICK SETUP

• The AD9260 Evaluation Board is configured as follows when

shipped:

1. 2.5 V external reference/4.0 V differential full-scale input:

JP5, JP9 and JP10 connected, JP6 and JP7 disconnected.

2. 8

× Mode/OSR: JP1 connected, JP2, JP3, and JP4

disconnected.

3. Full Speed Power Bias: R2 = 2 k

Ω and connected.

4. CSB pulled low: R6 = 49.9

Ω and connected, R29

disconnected.

5. RESETB pulled high: R7 = 10 k

Ω and connected, R30 dis-

connected.

6. READ pulled high: R28 = 10 k

Ω and connected, R5

disconnected.

7. Single Tone Input: JP8 removed, input applied via IN-1 (J7).

8. Input signal common-mode level set by Trimpot R35 to

2.0 V: Jumper JP12 is disconnected and resistors Rx4 and

Rx3 are connected.

9. AC Coupled Clock: JP12 connected and JP11 disconnected.

Note: 50

Ω terminated by R27.

QUICK SETUP

1. Connect the required power supplies to the Evaluation

Board as illustrated in Figure 22:

⇒±5 VA supplies to P5—Analog Power

⇒ +5 VA supply to P4—Analog Power

⇒ +5 VD supply to P3—Digital Power

⇒ +5 VD supply to P2—Driver Power

2. Connect a Clock Source to CLKIN (J1): Note: 50

Ω termi-

nated by R1.

3. Connect an Input Signal Source to the IN-1 (J7).

4. Turn On Power!

5. The AD9260 Evaluation Board is now ready for use.

APPLICATION TIPS

1. The ADC analog input should not be overdriven. Using a

signal amplitude slightly lower than FSR will allow a

small amount of “headroom” so that noise or DC offset

voltage will not overrange the ADC and “hard limit” on

signal peaks.

2. Two-tone tests can produce signal envelopes that exceed

FSR. Set each test signal to slightly less than –6 dB to pre-

vent “hard limiting” on peaks.

3. Bandpass filtering of test signal generators is absolutely

necessary for SNR, THD and IMD tests. Note, a low noise

signal generator along with a high Q bandpass filter is often

necessary to achieve the attainable noise performance of the

AD9260.

4. Test signal generators must have exceptional noise perfor-

mance to achieve accurate SNR measurements. Good gen-

erators, together with fifth-order elliptical bandpass filters,

are recommended for SNR tests. Narrow bandwidth crystal

filters can also be used to filter generator broadband noise,

but they should be carefully tested for operation at high-

signal levels.

5. The analog inputs of the AD9260 should be terminated

directly at the input pin sockets with the correct filter termi-

nating impedance (50

Ω or 75 Ω), or it should be driven by

a low output impedance buffer. Short leads are necessary to

prevent digital noise pickup.

6. A low noise (jitter) clock signal generator is required for

good ADC dynamic performance. A poor generator can

seriously impair good SNR performance particularly at

higher input frequencies. A high-frequency generator, based

on a clock source (e.g., crystal source), is recommended.

Frequency-synthesized clock generators should generally be

avoided because they typically provide poor jitter perfor-

mance. See Note 8 if a crystal-based clock generator is used

during FFT testing.

A low jitter clock may be generated by using a high-frequency

clock source and dividing this frequency down with a low noise

clock divider to obtain the AD9260 input CLK. Maintaining a

large amplitude clock signal may also be very beneficial in mini-

mizing the effects of noise in the digital gates of the clock gen-

eration circuitry.

Finally, special care should be taken to avoid coupling noise

into any digital gates preceding the AD9260 CLK pin. Short

leads are necessary to preserve fast rise times and careful decou-

pling should be used with these digital gates and the supplies

for these digital gates should be connected to the same supplies

as that of the internal AD9260 clock circuitry (Pins 44 and 38).

7. Two-tone testing will require isolation between test signal

generators to prevent IMD generation in the test generator

output circuits.

8. A very low side-lobe window must be used for FFT calcula-

tions if generators cannot be phase-locked and set to exact

frequencies.

9. A well designed, clean PC board layout will assure proper

operation and clean spectral response. Proper grounding

and bypassing, short lead lengths, separation of analog and

digital signals, and the use of ground planes are particularly

important for high-frequency circuits. Multilayer PC boards

are recommended for best performance, but if carefully

designed, a two-sided PC board with large heavy (20 oz.

foil) ground planes can give excellent results.

10. Prototype “plug-boards” or wire-wrap boards will not be

satisfactory.

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