AD9260EB datasheet(25/36 Pages) AD

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AD9260

–25–

REV. B

0.1 F

CAPT

CAPB

AD9260

0.1 F

10 F

0.1 F

VREF

SENSE

REFCOM

Figure 61. Recommended Reference Decoupling Network

DIGITAL INPUTS AND OUTPUTS

Digital Outputs

The AD9260 output data is presented in a twos complement

format. Table V indicates the output data formats for various

input ranges and decimation modes. A straight binary output

data format can be created by inverting the MSB.

Table V. Output Data Format

Input (V)

Condition (V)

Digital Output

Decimation Mode

VINA–VINB

< –0.8

× VREF

1000 0000 0000 0000

VINA–VINB

= –0.8

× VREF

1000 0000 0000 0000

VINA–VINB

= 0

0000 0000 0000 0000

VINA–VINB

= +0.8

× VREF – 1 LSB

0111 1111 1111 1111

VINA–VINB

>= + 0.8

× VREF

0111 1111 1111 1111

Decimation Mode

VINA–VINB

< –0.825

× VREF

1000 0001 0001 1100

VINA–VINB

= –0.825

× VREF

1000 0001 0000 1100

VINA–VINB

= 0

0000 0000 0000 0000

VINA–VINB

= +0.825

× VREF – 1 LSB 0111 1110 1110 0011

VINA–VINB

>= + 0.825

× VREF

0111 1110 1110 0011

Decimation Mode

VINA–VINB

< –0.825

× VREF

1000 0000 0100 0001

VINA–VINB

= –0.825

× VREF

1000 0000 0100 0001

VINA–VINB

= 0

0000 0000 0000 0000

VINA–VINB

= +0.825

× VREF – 1 LSB 0111 1111 1011 1110

VINA–VINB

>= + 0.825

× VREF

0111 1111 1011 1110

The slight different

± full-scale input voltage conditions and

their corresponding digital output code for the 4

× and 2× deci-

mation modes can be attributed to the different digital scaling

factors applied to each of the AD9260’s FIR decimation stages

for filter optimization purposes. Thus, a + full-scale reading of

0111 1111 1111 1111 and – full-scale reading of 1000 0000

0000 0000 is unachievable in the 2

× and 4× decimation mode.

As a result, a digital overrange condition can never exist in the

× and 4× decimation mode and thus OTR being set high indi-

cates an overrange condition in the analog modulator.

The output data format in 1

× decimation differs from that in 2×,

× and 8× decimation modes. In 1× decimation mode the out-

put data remains in a twos complement format, but the digital

numbers are scaled by a factor of 7/128. This factor of 7/128 is

the product of an internal scale factor of 7/8 in the analog modula-

tor and a 1/16 scale factor caused by LSB justification of the

12-bit modulator data.

CS AND READ PINS

The

CS and READ pins control the state of the output data

pins (BIT1–BIT16) on the AD9260. The

CS pin is active low

and the READ pin is active high. When

CS and READ are

both active the ADC data is driven on the output data pins,

otherwise the output data pins are in a high-impedance (Hi-Z)

state. Table VI indicates the relationship between the

CS and

READ pins and the state of Pins Bit 1–Bit 16.

Table VI.

CS and READ Pin Functionality

READ

Condition of Data Output Pins

Low

Data Output Pins in Hi-Z State

Low

High

ADC Data on Output Pins

High

Low

Data Output Pins in Hi-Z State

High

Data Output Pins in Hi-Z State

DAV PIN

The DAV pin indicates when the output data of the AD9260 is

valid. Digital output data is updated on the rising edge of DAV.

The data hold time (tH) is dependent on the external loading of

DAV and the digital data output pins (BIT1–BIT16) as well as

the particular decimation mode. The internal DAV driver is

sized to be larger than the drivers pertaining to the digital data

outputs to ensure that rising edge of DAV occurs before the

data transitions under similar loading conditions (i.e., fanout)

regardless of mode. Note that minimum data hold (tH) of 3.5 ns

is specified in the Figure 4 timing diagram from the 50% point

of DAV’s rising edge to the 50% of data transition using a ca-

pacitive load of 20 pF for DAV and BIT1–BIT16. Applications

interfacing to TTL logic and/or having larger capacitive loading

for DAV than BIT1–BIT16 should consider latching data on

the falling edge of DAV since the falling edge of DAV occurs

well after the data has transitioned in the case of the 2

×, 4× and

× modes. The duty cycle of DAV is approximately 50% and it

remains active independent of

CS and READ.

RESET PIN

The

RESET pin is an asynchronous digital input that is active

low. Upon asserting

RESET low, the clocks in the digital deci-

mation filters are disabled, the DAV pin goes low and the data

on the digital output data pins (Bit 1–Bit 16) is invalid. In addi-

tion, the analog modulator in the AD9260 and internal clock

dividers used in the decimation filters are reset and will remain

reset as long as

RESET is maintained low. In the 2

×, 4×, or 8×

mode, the

RESET must remain low for at least a clock period to

ensure all the clock dividers and analog modulator are reset.

Upon bringing

RESET high, the internal clock dividers will

begin to count again on the next falling edge of CLK and DAV

will go high approximately 15 ns after this falling edge, resuming

normal operation. Refer to Figure 4b for a timing diagram.

The state of the internal decimation filters in the AD9260

remains unchanged when

RESET is asserted low. Conse-

quently, when

RESET is pulsed low, this resets the analog

modulator but does not clear all the data in the digital filters.

The data in the filters is corrupted by the effect of resetting the

analog modulator (this causes an abrupt change at the input of

the digital filter and this change is unrelated to the signal at the

input of the A/D converter). Similarly, in multiplexed applica-

tions in which the input of the A/D converters sees an abrupt

change, the data in the analog modulator and digital filter will

be corrupted.

For this reason, following a pulse on the

RESET pin, or change

in channels (i.e., multiplexed applications only), the decimation

filters must be flushed of their data. These filters have a memory

length, hence delay, equal to the number of filter taps times

the clock rate of the converter. This memory length may be

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