AD9696 datasheet(4/8 Pages) AD

4 / 8 page

AD9696/AD9698

–4–

REV. B

PIN CONFIGURATIONS

AD9696KN/KR/KQ/TQ/TZ

Q1OUT (N/C)

Q1OUT (–VS)

GROUND (–IN1)

LATCH ENABLE 1 (+IN1)

N/C (+IN2)

–VS (–IN2)

–IN1 (+VS)

TOP VIEW

(Not to Scale)

+IN1 (N/C)

+IN2 (LATCH ENABLE 2)

–IN2 (GROUND)

N/C (Q2OUT)

LATCH ENABLE 2 (Q1OUT)

Q2OUT (GROUND)

Q2OUT (LATCH ENABLE 1)

AD9698KN/KQ/TQ

[AD9698KR/TZ PINOUTS SHOWN IN ( )]

GROUND (Q1OUT)

+VS (Q2OUT)

LATCH

ENABLE

TOP VIEW

(Not to Scale)

+VS

+IN

–IN

–VS

GROUND

QOUT

Name

Function

Q1OUT

One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at +IN1 is greater than voltage at

–IN1 and LATCH ENABLE 1 is at logic LOW.

Q1OUT

One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at –IN1 is greater than voltage at

+IN1 and LATCH ENABLE 1 is at logic LOW.

GROUND

Analog and digital ground return. All GROUND pins should be connected together and to a low impedance

ground plane near the comparator.

LATCH

Output at Q1OUT will track differential changes at the inputs when LATCH ENABLE 1 is at logic LOW.

ENABLE 1

When LATCH ENABLE 1 is at logic HIGH, the output at Q1OUT will reflect the input state at the application of

the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see

block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)

within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns.

N/C

No internal connection to comparator.

–VS

Negative power supply connection; nominally –5.2 V.

–IN1

Inverting input of differential input stage for Comparator #1.

+IN1

Noninverting input of differential input stage for Comparator #1.

+IN2

Noninverting input of differential input stage for Comparator #2.

–IN2

Inverting input of differential input stage for Comparator #2.

+VS

Positive power supply connection; nominally +5 V.

LATCH

Output at Q2OUT will track differential changes at the inputs when LATCH ENABLE 2 is at logic LOW.

ENABLE 2

When LATCH ENABLE 2 is at logic HIGH, the output at Q2OUT will reflect the input state at the application of

the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see

block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)

within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns.

Q2OUT

One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at –IN2 is greater than voltage at

+IN2 and LATCH ENABLE 2 is at logic LOW.

Q2OUT

One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at +IN2 is greater than voltage at

–IN2 and LATCH ENABLE 2 is at logic LOW.

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam-

age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

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