AD9826 datasheet(14/20 Pages) AD

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AD9826

–14–

REV. A

adjust pin. A voltage applied to this pin will be subtracted from

the voltages applied to the Red, Green, and Blue inputs in the first

amplifier stage of the AD9826. The input clamp is disabled in this

mode. For more information, see the Circuit Operation section.

Timing for this mode is shown in Figure 4. CDSCLK1 should

be grounded in this mode. The rising edge of CDSCLK2 should

not occur before the previous falling edge of ADCCLK, as shown

by tADC2. The output data latency is three ADCCLK cycles. The

offset and gain values for the Red, Green, and Blue channels are

programmed using the serial interface. The order in which the

channels are switched through the multiplexer is selected by

programming the MUX Configuration Register.

1-Channel CDS Mode

This mode operates the same way as the 3-Channel CDS mode.

The difference is that the multiplexer remains fixed in this mode,

so only the channel specified in the MUX Configuration Regis-

ter is processed.

Timing for this mode is shown in Figure 2.

1-Channel SHA Mode

This mode operates the same way as 3-Channel SHA mode,

except that the multiplexer remains stationary. Only the channel

specified in the MUX Configuration Register is processed.

Timing for this mode is shown in Figure 6. CDSCLK1 should

be grounded in this mode of operation.

Configuration Register

The Configuration Register controls the AD9826’s operating

mode and bias levels. Bits D8 and D1 should always be set low.

Table II. Configuration Register Settings

D8D7

Set

Input Range Internal VREF

3CH Mode

CDS Operation

Input Clamp Bias

Power-Down

Set

Output Mode

1 = 4 V

1 = Enabled

1 = On

1 = CDS Mode

1 = 4 V

1 = On

0 = 2 Byte

0 = 2 V

0 = Disabled

0 = Off

0 = SHA Mode

0 = 3 V

0 = Off (Normal)

1 = 1 Byte

*Power-on default value.

Bit D7 controls the input range of the AD9826. Setting D7 high

sets the input range to 4 V while setting Bit D7 low sets the

input range to 2 V. Bit D6 controls the internal voltage refer-

ence. If the AD9826’s internal voltage reference is used, then

this bit is set high. Setting Bit D6 low will disable the internal

voltage reference, allowing an external voltage reference to be

used. Setting Bit D5 high will configure the AD9826 for 3-

channel operation. If D5 is set low, the part will be in either

2CH or 1CH mode based on the settings in the MUX Configu-

ration Register (See Table III and the MUX Configuration

mode of operation, and setting this bit low will enable the SHA

mode of operation. Bit D3 sets the dc bias level of the AD9826’s

input clamp.

This bit should always be set high for the 4 V clamp bias, unless

a CCD with a reset feedthrough transient exceeding 2 V is used.

If the 3 V clamp bias level is used, then the peak-to-peak input

signal range to the AD9826 is reduced to 3 V maximum. Bit D2

controls the power-down mode. Setting Bit D2 high will place

the AD9826 into a very low-power “sleep” mode. All register

contents are retained while the AD9826 is in the powered-down

state. Bit D0 controls the output mode of the AD9826. Setting

Bit D0 high will enable a single byte output mode where only

the 8 MSBs of the 16 b ADC will be output on each rising edge

of ADCCLK (see Figure 8). If Bit D0 is set low, then the 16 b

ADC output is multiplexed into two bytes. The MSByte is

output on ADCCLK rising edge and the LSByte is output on

ADCCLK falling edge.

Table I. Internal Register Map

Address

Data Bits

Name

Configuration

Input Rng

VREF

3CH Mode

CDS On

Clamp

Pwr Dn

1 Byte Out

MUX Config

RGB/BGR

Red

Green

Blue

Red PGA

MSB

LSB

Green PGA

MSB

LSB

Blue PGA

MSB

LSB

Red Offset

MSB

LSB

Green Offset

MSB

LSB

Blue Offset

MSB

LSB

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