AD9826 datasheet(17/20 Pages) AD

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AD9826

–17–

REV. A

Analog Inputs—

SHA Mode Operation

Figure 14 shows the analog input configuration for the SHA

mode of operation. Figure 15 shows the internal timing for the

sampling switches. The input signal is sampled when CDSCLK2

transitions from high to low, opening S1. The voltage on the

OFFSET pin is also sampled on the falling edge of CDSCLK2,

when S2 opens. S3 is then closed, generating a differential out-

put voltage representing the difference between the sampled

input voltage and the OFFSET voltage. The input clamp is

disabled during SHA mode operation.

INPUT

SIGNAL

CML

VINR

AD9826

OFFSET

4pF

OPTIONAL DC

OFFSET (OR

CONNECT

TO GND)

VING

VINB

Figure 14. SHA-Mode Input Configuration (All Three

Channels Are Identical)

CDSCLK2

(INTERNAL)

S3 OPEN

S1, S2 OPEN

S1, S2 CLOSED

S3 CLOSED

Figure 15. SHA-Mode Internal Switch Timing

Figure 16 shows how the OFFSET pin may be used in a CIS

application for coarse offset adjustment. Many CIS signals have

dc offsets ranging from several hundred millivolts to more than

1 V. By connecting the appropriate dc voltage to the OFFSET

pin, the CIS signal will be restored to “zero.” After the large dc

offset is removed, the signal can be scaled using the PGA to

maximize the ADC’s dynamic range.

SHA

VINR

VING

VINB

OFFSET

RED

GREEN

BLUE

VRED FROM

CIS MODULE

AVDD

DC OFFSET

RED-

OFFSET

GREEN-

OFFSET

BLUE-

OFFSET

AD9826

0.1 F

Figure 16. SHA-Mode Used with External DC Offset

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