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STM32F407IG Datasheet(PDF) 125 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 125 Page - STMicroelectronics |
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125 / 180 page ![]() STM32F405xx, STM32F407xx Electrical characteristics Doc ID 022152 Rev 3 125/180 tlatr (4) Regular trigger conversion latency fADC = 30 MHz - - 0.067 µs -- 2(7) 1/fADC tS (4) Sampling time fADC = 30 MHz 0.100 - 16 µs 3 - 480 1/fADC tSTAB (4) Power-up time - 2 3 µs tCONV (4) Total conversion time (including sampling time) fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC fS (4) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+ (4) ADC VREF DC current consumption in conversion mode fADC = 30 MHz 3 sampling time 12-bit resolution - 300 500 µA fADC = 30 MHz 480 sampling time 12-bit resolution -- 16 µA IVDDA (4) ADC VDDA DC current consumption in conversion mode fADC = 30 MHz 3 sampling time 12-bit resolution -1.6 1.8 mA fADC = 30 MHz 480 sampling time 12-bit resolution -- 60 µA 1. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced temperature range (0 to 70 °C). 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. VDDA -VREF+ < 1.2 V. 4. Based on characterization, not tested in production. 5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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