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STM32F407IG Datasheet(PDF) 133 Page - STMicroelectronics

Part # STM32F407IG
Description  ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  180 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F407IG Datasheet(HTML) 133 Page - STMicroelectronics

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STM32F405xx, STM32F407xx
Electrical characteristics
Doc ID 022152 Rev 3
133/180
Figure 53.
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1.
Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 73.
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)
1.
CL = 30 pF.
2.
Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
2THCLK–0.5 2 THCLK+1
ns
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
0.5
3
ns
tw(NOE)
FSMC_NOE low time
2THCLK–2
2THCLK+ 2
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
0
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
4.5
ns
th(A_NOE)
Address hold time after FSMC_NOE high
4
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
1.5
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0
-
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
THCLK+4
-
ns
tsu(Data_NOE)
Data to FSMC_NOEx high setup time
THCLK+4
-
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
2
ns
tw(NADV)
FSMC_NADV low time
-
THCLK
ns



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