ADG428 datasheet(6/12 Pages) AD

6 / 12 page

REV. C

ADG428/ADG429

–6–

TIMING DIAGRAMS

A0, A1, (A2)

50%

0.8V

Figure 1.

Figure 1 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive; there-

fore, while

WR is held low, the latches are transparent and the

switches respond to the address and enable inputs. This input

data is latched on the rising edge of

WR.

50%

SWITCH

OUTPUT

0.8VO

tRS

tOFF (RS)

Figure 2.

Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff

Time, tOFF, (RS).

Note: All digital input signals rise and fall times are measured

from 10% to 90% of 3 V. tr = tf = 20 ns.

Typical Characteristics

VD (VS) – Volts

140

–15

–10

–5

130

100

VDD = +15V

VSS = –15V

120

110

TA = +25 C

VDD = +5V

VSS = –5V

VDD = +12V

VSS = –12V

VDD = +10V

VSS = –10V

Figure 3. RON as a Function of VD (VS): Dual Supply

Voltage

VD (VS) – Volts

–15

–10

–5

VDD = +15V

VSS = –15V

+125 C

+85 C

+25 C

Figure 4. RON as a Function of VD (VS) for Different

Temperatures

VD (VS) – Volts

600

550

100

015

400

250

200

150

500

450

300

350

TA = +25 C

VDD = +12V

VSS = 0V

VDD = +10V

VSS = 0V

VDD = +5V

VSS = 0V

VDD = +15V

VSS = 0V

Figure 5. RON as a Function of VD (VS): Single Supply

Voltage

VD (VS) – Volts

160

015

468

150

120

140

130

110

100

VDD = +12V

VSS = 0V

+125 C

+25 C

+85 C

Figure 6. RON as a Function of VD (VS) for Different

Temperatures

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