ADG508F/ADG509F/ADG528F

REV. C

–3–

Table I. ADG508F Truth Table

A2

A1

A0

EN

ON SWITCH

X

X

X

0

NONE

00011

00112

01013

01114

10015

10116

11017

11118

X = Don’t Care

Table II. ADG509F Truth Table

A1

A0

EN

ON SWITCH PAIR

X

X

0

NONE

0011

0112

1013

1114

X = Don’t Care

Table III. ADG528F Truth Table

ON

A2

A1

A0

EN

WR

RS

SWITCH

X

XXX

g

1

Retains Previous Switch Condition

X

XXXX0

NONE (Address and Enable Latches Cleared)

X

X

X

0

0

1

NONE

0

00101

1

0

01101

2

0

10101

3

0

11101

4

1

00101

5

1

01101

6

1

10101

7

1

11101

8

X = Don’t Care

TIMING DIAGRAMS (ADG528F)

50%

50%

0.8V

2V

3V

WR

0V

3V

0V

A0, A1, A2

EN

Figure 1.

Figure 1 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive; there-

fore, while WR is held low, the latches are transparent and the

switches respond to the address and enable inputs. This input

data is latched on the rising edge of WR.

50%

50%

3V

RS

0V

SWITCH

OUTPUT

0V

Figure 2.

Note: All digital input signals rise and fall times are measured