ADG725/ADG731

–7–

REV. PrD

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTION

ADG725

ADG731

Mnemonic Function

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of

the serial clock input. These devices can accomodate serial input rates of up to

30MHz.

RS

Active low control input that clears the input register and turns all switches to the

OFF condition.

D I N

Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of

the serial clock input.

S X X

Source. May be an input or output.

D X

Drain. May be an input or output.

Power Supply Input. These parts can be operated from a supply of +1.8V to +5.5V

and dual supply of +/-2.5V.

G N D

Ground reference.

SYNC

Active Low Control Input. This is the frame synchronization signal for the input

data. When

SYNC goes low, it powers on the SCLK and DIN buffers and the input

shift register is enabled. An 8-bit counter is also enabled. Data is transferred on the

falling edges of the following clocks. After 8 falling clock edges, switch conditions

are automaticaly updated.

SYNC may be used to frame the signal, or just pulled low

for a short period of time to enable the counter and input buffers.

PIN CONFIGURATIONS

CSP & TQFP

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

S28

S27

S26

S25

S24

S23

S22

S12

S11

S10

S9

S8

S7

S6

NC = NO CONNECT

S5

S4

S3

S2

S21

S20

S19

S18

ADG731

S1

S17

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

S12B

S11B

S10B

S9B

S8B

S7B

S6B

S12A

S11A

S10A

S9A

S8A

S7A

S6A

NC = NO CONNECT

S5A

S4A

S3A

S2A

S5B

S4B

S3B

S2B

ADG725

S1A

S1B