ADG728 datasheet(4/12 Pages) AD

4 / 12 page

–4–

REV. 0

ADG728/ADG729

TIMING CHARACTERISTICS1

Parameter

Limit at TMIN, TMAX

Unit

Conditions/Comments

fSCL

400

kHz max

SCL Clock Frequency

2.5

ms min

SCL Cycle Time

0.6

ms min

tHIGH, SCL High Time

1.3

ms min

tLOW, SCL Low Time

0.6

ms min

tHD, STA, Start/Repeated Start Condition Hold Time

100

ns min

tSU, DAT, Data Setup Time

0.9

ms max

tHD, DAT, Data Hold Time

0ms min

0.6

ms min

tSU, STA, Setup Time for Repeated Start

0.6

ms min

tSU, STO, Stop Condition Setup Time

1.3

ms min

tBUF, Bus Free Time Between a STOP Condition and

a Start Condition

t10

300

ns max

tR, Rise Time of Both SCL and SDA when Receiving

20 + 0.1Cb

ns min

t11

250

ns max

tF, Fall Time of SDA when Receiving

300

ns max

tF, Fall Time of SDA when Transmitting

20 + 0.1Cb

ns min

400

pF max

Capacitive Load for Each Bus Line

tSP

ns max

Pulsewidth of Spike Suppressed

NOTES

1See Figure 1.

2A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

IH min of the SCL signal) in order to bridge the undeﬁned region of

the falling edge of SCL.

b is the total capacitance of one bus line in pF. t R and tF measured between 0.3 VDD and 0.7 VDD.

4Input ﬁltering on both the SCL and SDA inputs suppress noise spikes which are less than 50 ns.

Speciﬁcations subject to change without notice.

t11

t10

SDA

SCL

START

CONDITION

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

Figure 1. 2-Wire Serial Interface Timing Diagram

(VDD = 2.7 V to 5.5 V. All speciﬁcations –40 C to +85 C, unless otherwise noted.)

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