PCM5142 datasheet(9/110 Pages) TI1

9 / 110 page

PCM5141, PCM5142

www.ti.com

SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS

All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless

otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

Bits

Data Format (PCM Mode)

Audio data interface format

I2S, left justified, right justified and TDM

Audio data bit length

16, 24, 32-bit acceptable

Audio data format

MSB First, 2s Complement

(1)

Sampling frequency

384

kHz

Clocks

System clock frequency

64, 128, 192, 256, 384, 512, 768, 1024, 1152,

1536, 2048, or 3072

fSCK, up to 50Mhz

Clock divider uses fractional divide

6.7

MHz

D > 0, P=1

PLL Input Frequency

(SCL Clock Frequency 400 kHz)

Clock divider uses integer divide

MHz

D = 0, P=1

Digital Input/Output

Logic Family: 3.3V LVCMOS compatible

VIH

0.7×DVDD

Input logic level

VIL

0.3×DVDD

IIH

VIN = VDD

Input logic current

µA

IIL

VIN = 0V

–10

VOH

IOH = –4mA

0.8×DVDD

Output logic level

VOL

IOL = 4mA

0.22×DVD

Logic Family 1.8V LVCMOS compatible

VIH

0.7×DVDD

Input logic level

VIL

0.3×DVDD

IIH

VIN = VDD

Input logic current

µA

IIL

VIN = 0V

–10

VOH

IOH = –2mA

0.8×DVDD

Output logic level

VOL

IOL = 2mA

0.22×DVD

(1)

One sample time si defined as the reciprocal of the sampling frequency. 1tS = 1/fS

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