ADSP-2189M datasheet(4/32 Pages) AD

4 / 32 page

REV. A

ADSP-2189M

–4–

functionality is reconfigurable, the default state is shown in plain

text; alternate functionality is shown in italics.

Common-Mode Pins

# of

Name(s)

Pins I/O Function

RESET

Processor Reset Input

Bus Request Input

Bus Grant Output

BGH

Bus Grant Hung Output

DMS

Data Memory Select Output

PMS

Program Memory Select Output

IOMS

Memory Select Output

BMS

Byte Memory Select Output

CMS

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

IRQ2

Edge- or Level-Sensitive Interrupt

Requests

PF7

I/O Programmable I/O Pin.

IRQL1

Level-Sensitive Interrupt Requests

PF6

I/O Programmable I/O Pin

IRQL0

Level-Sensitive Interrupt Requests

PF5

I/O Programmable I/O Pin

IRQE

Edge-Sensitive Interrupt Requests

PF4

I/O Programmable I/O Pin

Mode D

Mode Select Input—Checked Only

During

RESET

PF3

I/O Programmable I/O Pin During

Normal Operation

Mode C

Mode Select Input—Checked Only

During

RESET

PF2

I/O Programmable I/O Pin During

Normal Operation

Mode B

Mode Select Input—Checked

Only During

RESET

PF1

I/O Programmable I/O Pin During

Normal Operation

Mode A

Mode Select Input—Checked Only

During

RESET

PF0

I/O Programmable I/O Pin During

Normal Operation

CLKIN, XTAL 2

Clock or Quartz Crystal Input

CLKOUT

Processor Clock Output

SPORT0

I/O Serial Port I/O Pins

SPORT1

I/O Serial Port I/O Pins

IRQ1:0, FI, FO

Edge- or Level-Sensitive Interrupts,

Flag In, Flag Out

PWD

Power-Down Control Input

PWDACK

Power-Down Control Output

FL0, FL1, FL2 3

Output Flags

VDDINT

Internal VDD (2.5 V) Power

VDDEXT

External VDD (2.5 V or 3.3 V)

Power

GND

Ground

EZ-Port

I/O For Emulation Use

NOTES

1Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to

enable the corresponding interrupts, then the DSP will vector to the appropri-

ate interrupt vector address when the pin is asserted, either by external devices,

or set as a programmable flag.

2SPORT configuration determined by the DSP System Control Register. Soft-

ware configurable.

Memory Interface Pins

The ADSP-2189M processor can be used in one of two modes,

Full Memory Mode, which allows BDMA operation with full

external overlay memory and I/O capability, or Host Mode,

which allows IDMA operation with limited external addressing

capabilities. The operating mode is determined by the state of

the Mode C pin during

RESET and cannot be changed while

the processor is running.

Full Memory Mode Pins (Mode C = 0)

# of

Name

Pins

I/O

Function

A13:0

Address Output Pins for Program,

Data, Byte and I/O Spaces

D23:0

I/O

Data I/O Pins for Program, Data,

Byte and I/O Spaces (8 MSBs are

also used as Byte Memory addresses.)

Host Mode Pins (Mode C = 1)

# of

Name

Pins

I/O

Function

IAD15:0

I/O

IDMA Port Address/Data Bus

Address Pin for External I/O,

Program, Data, or Byte Access

D23:8

I/O

Data I/O Pins for Program, Data

Byte and I/O Spaces

IWR

IDMA Write Enable

IRD

IDMA Read Enable

IAL

IDMA Address Latch Pin

IDMA Select

IACK

IDMA Port Acknowledge Config-

urable in Mode D; Open Drain

NOTE

1In Host Mode, external peripheral addresses can be decoded using the A0,

CMS, PMS, DMS and IOMS signals.

Interrupts

The interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

The ADSP-2189M provides four dedicated external interrupt

input pins,

IRQ2, IRQL0, IRQL1 and IRQE (shared with the

PF7:4 pins). In addition, SPORT1 may be reconfigured for

IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six

external interrupts. The ADSP-2189M also supports internal

interrupts from the timer, the byte DMA port, the two serial

ports, software and the power-down control circuit. The inter-

rupt levels are internally prioritized and individually maskable

(except power-down and reset). The

IRQ2, IRQ0 and IRQ1

input pins can be programmed to be either level- or edge-sensi-

tive.

IRQL0 and IRQL1 are level-sensitive and IRQE is edge-

sensitive. The priorities and vector addresses of all interrupts are

shown in Table I.

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