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ADV601LC

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Host Interface Pins

(Continued)

Name

Pins

I/O

Description

ACK

Host Acknowledge. The ADV601LC acknowledges completion of a Host Interface

access by asserting this pin. Most Host Interface accesses (other than the com-

pressed data register access) result in ACK being held high for at least one wait

cycle, but some exceptions to that rule are as follows:

•

A full FIFO during decode operations causes the ADV601LC to de-assert

•

(drive HI) the ACK pin, holding off further writes of compressed data until

•

the FIFO has one available location.

•

An empty FIFO during encode operations causes the ADV601LC to de-assert

(drive HI) the ACK pin, holding off further reads until one location is filled.

FIFO_SRQ

FIFO Service Request. This pin is an active high signal indicating that the FIFO

needs to be serviced by the host. (see FIFO Control register). The state of this pin

also appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a

Host interrupt (HIRQ pin) based on the state of the FIFO_SRQ pin. This pin oper-

ates as follows:

•

LO No FIFO Service Request condition (FIFOSRQ bit LO)

•

HI FIFO needs service is nearly full (encode) or nearly empty (decode)

During encode, FIFO_SRQ is LO when the SWR bit is cleared (0) and goes HI

when the FIFO is nearly full (see FIFO Control register).

During decode, FIFO_SRQ is HI when the SWR bit is cleared (0), because FIFO

is empty, and goes LO when the FIFO is filled beyond the nearly empty condition

(see FIFO Control register).

STATS_R

Statistics Ready. This pin indicates the Wavelet Statistics (contents of Sum of

Squares, Sum of Value, MIN Value, MAX Value registers) have been updated and

are ready for the Bin Width calculator to read them from the host interface. The

frequency of this interrupt will be equal to the field rate. The state of this pin also

appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a

Host interrupt (HIRQ pin) based on the state of the STATS_R pin. This pin oper-

ates as follows:

•

LO No Statistics Ready condition (STATSR bit LO)

•

HI Statistics Ready for BW calculator (STATSR bit HI)

LCODE

Last Compressed Data (for field). This bit indicates the last compressed data word

for field will be retrieved from the FIFO on the next read from the host bus. The

frequency of this interrupt is similar to the field rate, but varies depending on

compression and host response. The state of this pin also appears in the Interrupt

Mask/Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin)

based on the state of the LCODE pin. This pin operates as follows:

•

LO No Last Code condition (LCODE bit LO)

•

HI Last data word for field has been read from FIFO (LCODE bit HI)

HIRQ

Host Interrupt Request. This pin indicates an interrupt request to the Host. The

Interrupt Mask/Status register can select conditions for this interrupt based on any

or all of the following: FIFOSTP, FIFOSRQ, FIFOERR, LCODE, STATR or

CCIR-656 unrecoverable error. Note that the polarity of the HIRQ pin can be

modified using the Mode Control register.

RESET

ADV601LC Chip Reset. Asserting this pin returns all registers to reset state. Note

that the ADV601LC must be reset at least once after power-up with this active low

signal input. For more information on reset, see the SWR bit description.

Power Supply Pins

Name

Pins

I/O

Description

GND

Ground

VDD

+5 V dc Digital Power

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