ADV601LC datasheet(20/44 Pages) AD

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ADV601LC

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Table VII. Component Digital Video Formats

Nominal

Bit/

Color

Data Rate

Master/

Format

Name

Component

Space

Sampling

(MHz)

Slave

I/F Width

Number

CCIR-656

YCrCb

4:2:2

Master

0x0

Multiplex Philips

YUV

4:2:2

<=29.5

Either

0x2

Clocks and Strobes

All video data is synchronous to the video clock (VCLK).

The rising edge of VCLK is used to clock all data into the

ADV601LC.

Synchronization and Blanking Pins

Three signals, which can be configured as inputs or outputs, are

used for video frame and field horizontal synchronization and

blanking. These signals are VSYNC, HSYNC, and FIELD.

VDATA Pins Functions With Differing Video Interface Formats

The functionality of the Video Interface pins depends on the

current video format. Table VIII defines how Video data pins

are used for the various formats.

Table VIII. VDATA[7:0] Pin Functions Under CCIR-656

and Multiplex Philips

VDATA[7:0] Pins

CCIR-656

Multiplex Philips

Data9

Data8

Data7

Data6

Data5

Data4

Data3

Data2

Video Formats—CCIR-656

The ADV601LC supports a glueless video interface to CCIR-656

devices when the Video Format is programmed to CCIR-656

mode. CCIR-656 requires that 4:2:2 data (8 bits per compo-

nent) be multiplexed and transmitted over a single 8-bit physical

interface. A 27 MHz clock is transmitted along with the data.

This clock is synchronous with the data. The color space of

CCIR-656 is YCrCb.

When in master mode, the CCIR-656 mode does not require

any external synchronization or blanking signals to accompany

digital video. Instead, CCIR-656 includes special time codes in

the stream syntax that define horizontal blanking periods, verti-

cal blanking periods, and field synchronization (horizontal and

vertical synchronization information can be derived). These

time codes are called End-of-Active-Video (EAV) and Start-of-

Active-Video (SAV). Each line of video has one EAV and one

SAV time code. EAV and SAV have three bits of embedded

information to define HSYNC, VSYNC and Field information

as well as error detection and correction bits.

VCLK is driven with a 27 MHz, 50% duty cycle clock which is

synchronous with the video data. Video data is clocked on the

rising edge of the VCLK signal. When decoding, the VCLK

signal is typically transmitted along with video data in the

CCIR-656 physical interface.

Electrically, CCIR-656 specifies differential ECL levels to be

used for all interfaces. The ADV601LC, however, only supports

unipolar, TTL logic thresholds. Systems designs that interface

to strictly conforming CCIR-656 devices (especially when inter-

facing over long cable distances) must include ECL level shifters

and line drivers.

The functionality of HSYNC, VSYNC and FIELD Pins is

dependent on three programmable modes of the ADV601LC:

Master-Slave Control, Encode-Decode Control and 525-625

Control. Table IX summarizes the functionality of these pins in

various modes.

Table IX. CCIR-656 Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality

HSYNC, VSYNC and FIELD

Master Mode (HSYNC, VSYNC

Slave Mode (HSYNC, VSYNC

Functionality for CCIR-656

and FIELD Are Outputs)

and FIELD Are Inputs)

Encode Mode (video data is input

Pins are driven to reflect the states of the

Undefined—Use Master Mode

to the chip)

received time codes: EAV and SAV. This

functionality is independent of the state of

the 525-625 mode control. An encoder is

most likely to be in master mode.

Decode Mode (video data is output

Pins are output to the precise timing definitions

Undefined—Use Master Mode

from the chip)

for CCIR-656 interfaces. The state of the pins

reflect the state of the EAV and SAV timing

codes that are generated in the output video data.

These definitions are different for 525 and 625 line

systems. The ADV601LC completely manages the

generation and timing of these pins.

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