ADV601LC

–32–

REV. 0

TIMING PARAMETERS

This section contains signal timing information for the ADV601LC. Timing descriptions for the following items appear in this

section:

• Clock signal timing

• Video data transfer timing (CCIR-656, and Multiplexed Philips formats)

• Host data transfer timing (direct register read/write access)

Clock Signal Timing

The diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin

loading of 50 pF.

Table XVIII. Video Clock Period, Frequency, Drift and Jitter

Min VCLK_CYC

Nominal VCLK_CYC

Max VCLK_CYC

Video Format

Period

Period (Frequency)

Period

1, 2

CCIR-601 PAL

35.2 ns

37 ns (27 MHz)

38.9 ns

CCIR-601 NTSC

35.2 ns

37 ns (27 MHz)

38.9 ns

NOTES

± 0.1 (VCLK_CYC/field.

Table XIX. Video Clock Duty Cycle

Min

Nominal

Max

VCLK Duty Cycle

1

(40%)

(50%)

(60%)

NOTE

Table XX. Video Clock Timing Parameters

Parameter

Description

Min

Max

Unit

VCLK Signal, Cycle Time (1/Frequency) at 27 MHz

(See Video Clock Period Table)

VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz

10

29

ns

VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz

10

29

ns

TEST CONDITIONS

Figure 18 shows test condition voltage reference and device

loading information. These test conditions consider an output

as disabled when the output stops driving and goes from the

measured high or low voltage to a high impedance state. Tests

reference input signal crossing +1.5 V and the time that the

output reaches the high impedance state (also +1.5 V). Simi-

larly, these tests conditions consider an output as enabled when

the output leaves the high impedance state and begins driving a

measured high or low voltage. Tests measure output enable time

+1.5 V and the time that the output reaches the measured high

or low voltage.

INPUT

REFERENCE

SIGNAL

OUTPUT

SIGNAL

t

DISABLED

t

ENABLED

1.5V

1.5V

INPUT & OUTPUT VOLTAGE/TIMING REFERENCES

DEVICE LOADING FOR AC MEASUREMENTS

TO

OUTPUT

PIN

2pF

+1.5V

Figure 18. Test Condition Voltage Reference and Device Loading