ADV7152

–5–

REV. B

PIXEL INPUT

DATA*

CLOCK

LOADOUT

LOADIN

ANALOG

OUTPUT

DATA

t

10

DIGITAL

INPUT TO ANALOG

OUTPUT

PIPELINE

t

PD

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK

IOR, IOR

IOG, IOG

IOB, IOB

I

Figure 4. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)

PIXEL INPUT

DATA*

CLOCK

LOADOUT

LOADIN

ANALOG

OUTPUT

DATA

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); SYNC; BLANK

DIGITAL

INPUT

TO ANALOG

OUTPUT

PIPELINE

t

PD

τ

τ- t

11

IOR, IOR

IOG, IOG

IOB, IOB

I

Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)

t

12

CLOCK

PRGCKOUT

(CLOCK/4)

PRGCKOUT

(CLOCK/8)

PRGCKOUT

(CLOCK/16)

PRGCKOUT

(CLOCK/32)

*INLCUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK

Figure 6. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT)