ADV7152LS85 datasheet(12/32 Pages) AD

12 / 32 page

ADV7152

–12–

REV. B

Alternatively, the ADV7152 CLOCK inputs can be driven by a

Programmable Clock Generator (Figure 13), such as the

ICS1562. The ICS1562 is a monolithic, phase-locked-loop,

clock generator chip. It is capable of synthesizing differential

ECL output frequencies in a range up to 220 MHz from a single

low frequency reference crystal.

GND

220

Ω

330

Ω

GND

+5V

CLOCK

GND

ADV7152

GND

D0–D3

CS R/W

ECL

OUT+

REF OUT

REF

+5V

CLOCK

0.1

µF

LOW FREQUENCY

OSCILLATOR

GND

220

Ω

330

Ω

ECL

OUT–

CLOCK

GENERATOR

Figure 13. PLL Generator Driving CLOCK, CLOCK of the

ADV7152

CLOCK CONTROL SIGNALS LOADOUT

The ADV7152 generates a LOADOUT control signal which

runs at a divided down frequency of the pixel CLOCK. The

frequency is automatically set to the programmed multiplex

rate, controlled by CR36 of Command Register 3.

fLOADOUT = fCLOCK/2

2:1 Multiplex Mode

fLOADOUT = fCLOCK

1:1 Multiplex Mode

The LOADOUT signal is used to directly drive the LOADIN

pixel latch signal of the ADV7152. This is most simply achieved

by tying the LOADOUT and LOADIN pins together. Alterna-

tively, the LOADOUT signal can be used to drive the frame

buffer’s shift clock signals, returning to the LOADIN input de-

layed with respect to LOADOUT.

LOADOUT

LOADIN

ADV7152

VIDEO

FRAME

BUFFER

LOADOUT

LOADIN

ADV7152

VIDEO

FRAME

BUFFER

LOADOUT(1)

LOADOUT(2)

PIXEL

DATA

PIXEL

DATA

LOADOUT(1)

LOADIN

LOADOUT(2)

LOADOUT

DELAY

Figure 14. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)

If it is not necessary to have a known fixed number of pipeline

delays, then there is no limitation on the delay between LOAD-

OUT and LOADIN (LOADOUT(1) and LOADOUT(2)).

LOADIN and Pixel Data must conform to the setup and hold

times (t8 and t9).

If however, it is required that the ADV7152 has a fixed number

of pipeline delays (tPD), LOADOUT and LOADIN must con-

form to timing specifications t10 and

τ-t

11 as illustrated in Fig-

ures 4 and 5.

PRGCKOUT

The PRGCKOUT control signal outputs a user programmable

clock frequency. It is a divided down frequency of the pixel

CLOCK (see Figure 8). The rising edge of PRGCKOUT is

synchronous to the rising edge of LOADOUT

fPRGCKOUT = f CLOCK/N

where N = 4, 8, 16 or 32.

One application of the PRGCKOUT is to use it as the master

clock frequency of the graphics subsystems processor or

controller.

SCKIN, SCKOUT

These video memory signals are used to minimize external sup-

port chips. Figure 15 illustrates the function that is provided.

An input signal applied to SCKIN is synchronously AND-ed

with the video blanking signal (BLANK). The resulting signal is

output on SCKOUT. Figure 7 of the Timing Waveform section

shows the relationship between SCKOUT, SCKIN and

BLANK

SCKOUT

SCKIN

BLANK

LATCH

ENABLE

SYNC

Figure 15. SCKOUT Generation Circuit

The SCKOUT signal is essentially the video memory shift con-

trol signal. It is stopped during the screen retrace. Figure 16

shows a suggested frame buffer to ADV7152 interface. This is a

minimum chip solution and allows the ADV7152 control the

overall graphics system clocking and synchronization.

LOADOUT

SCKOUT

ADV7152

VIDEO

FRAME

BUFFER

PIXEL

DATA

LOADIN

SCKIN

BLANK

Figure 16. ADV7152 Interface Using SCKIN and SCKOUT

ADV7152LS85 Datasheet(PDF) 12 Page - Analog Devices

ADV7152LS85 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL