ADV7177 datasheet(6/38 Pages) AD

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ADV7177/ADV7178

–6–

REV. 0

5 V TIMING SPECIFICATIONS

(VAA = 4.75 V – 5.25 V

1, V

REF = 1.235 V, RSET = 300

. All specifications TMIN to TMAX

2 unless

otherwise noted.)

Parameter

Conditions

Min

Typ

Max

Units

MPU PORT

3, 4

SCLOCK Frequency

100

kHz

SCLOCK High Pulsewidth, t1

4.0

µs

SCLOCK Low Pulsewidth, t2

4.7

µs

Hold Time (Start Condition), t3

After This Period the First Clock Is Generated

4.0

µs

Setup Time (Start Condition), t4

Relevant for Repeated Start Condition

4.7

µs

Data Setup Time, t5

250

SDATA, SCLOCK Rise Time, t6

µs

SDATA, SCLOCK Fall Time, t7

300

Setup Time (Stop Condition), t8

4.7

µs

ANALOG OUTPUTS

3, 5

Analog Output Delay

5ns

DAC Analog Output Skew

CLOCK CONTROL

AND PIXEL PORT

3, 6

fCLOCK

MHz

Clock High Time, t9

8ns

Clock Low Time, t10

8ns

Data Setup Time, t11

3.5

Data Hold Time, t12

4ns

Control Setup Time, t11

4ns

Control Hold Time, t12

3ns

Digital Output Access Time, t13

Digital Output Hold Time, t14

4ns

Pipeline Delay, t15

Clock Cycles

RESET CONTROL

3, 4

RESET Low Time

INTERNAL CLOCK CONTROL

Clock/2 Rise Time, t16

7ns

Clock/2 Fall Time, t17

7ns

OSD TIMING

OSD Setup Time, t18

6ns

OSD Hold Time, t19

2ns

NOTES

1The max/min specifications are guaranteed over this range.

2Temperature range T

MIN to TMAX: 0°C to +70°C.

3TTL input values are 0 to 3 volts, with input rise/fall times

≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load

≤ 10 pF.

4Guaranteed by characterization.

5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6Pixel Port consists of the following:

Pixel Inputs:

P15–P0

Pixel Controls:

HSYNC, FIELD/VSYNC, BLANK

Clock Input:

CLOCK

Specifications subject to change without notice.

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