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18

HMC1197LP7FE

v00.0912

WIDEBAND DIRECT QUADRATURE MODULATOR

w/ FRACTIONAL-N PLL & VCO, 100 - 4000 MHz

Reg 06h Delta Sigma Modulator Register

BIT

TYPE

NAME

W

DEFLT

DESCRIPTION

[1:0]

R/W

Reserved

2

2d

Reserved, Program to 0h

[3:2]

R/W

DSM Order

2

2d

Select the Delta Sigma Modulator Type

0: 1st order

1: 2nd Order

2: 3rd Order - Recommended

3: Reserved

[4]

R/W

Synchronous SPI Mode

1

0

0: Normal SPI Load - all register load on rising edge of SEN

to load synchronously on the next internal clock cycle.

Normally (When this bit is 0) SPI writes into the internal state

machines/counters happen asynchronously relative to the internal

clocks. This can create freq/phase disturbances if writing register

3, 4 or 1A. When this bit is enabled, the internal SPI registers are

loaded synchronously with the internal clock. This means that

the data in the SPI shifter should be held constant for at least 2

PFD clock periods after SEN is asserted to allow this retiming to

happen cleanly.

[5]

R/W

Exact Frequency Mode Enable

1

0

1: Exact Frequency Mode Enabled

0: Exact Frequency Mode Disabled

[6]

R/W

Reserved

1

0

Reserved

[7]

R/W

Fractional Bypass

1

0

0: Use Modulator, Required for Fractional Mode,

1: Bypass Modulator, Required for Integer Mode

Note: When enabled fractional modulator output is ignored, but

fractional modulator continues to be clocked if Reg 06h[11] =1.

This feature can be used to test the isolation of the digital frac-

tional modulator from the VCO output in integer mode.

[8]

R/W

Autoseed EN

1

1

1: loads the modulator seed (start phase) whenever the fractional

register (Reg 04h) is written

0: when fractional register (Reg 04h) write changes frequency,

modulator starts at previous value (phase)

[10:9]

R/W

Reserved

2

3d

Reserved

[11]

R/W

Delta Sigma Modulator Enable

1

1

0: Disable DSM, used for Integer Mode

1: Enable DSM Core, required for Fractional Mode

[22:12]

R/W

Reserved

11

97d

61h

Reserved, Program to 30h