LTC3835 datasheet(29/40 Pages) LINER

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LTC3890-3

38903f

For more information www.linear.com/3890-3

applicaTions inForMaTion

4. Are the SENSE– and SENSE+ leads routed together with

minimumPCtracespacing?Thefiltercapacitorbetween

SENSE+ and SENSE– should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the SENSE resistor.

5. Is the INTVCC decoupling capacitor connected close

to the IC, between the INTVCC and the power ground

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1µF ceramic capacitor placed

immediately next to the INTVCCandPGNDpinscanhelp

improve noise performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from

the opposites channel’s voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the output side of the LTC3890-3 and occupy minimum

PC trace area.

7. Use a modified star ground technique: a low impedance,

large copper area central grounding point on the same

side of the PC board as the input and output capacitors

with tie-ins for the bottom of the INTVCC decoupling

capacitor, the bottom of the voltage feedback resistive

divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductorwhiletestingthecircuit.Monitortheoutputswitch-

ing node (SW pin) to synchronize the oscilloscope to the

internal oscillator and probe the actual output voltage as

well. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 25% of the maximum designed current level in

Burst Mode operation.

Thedutycyclepercentageshouldbemaintainedfromcycle

to cycle in a well-designed, low noise PCB implementa-

tion. Variation in the duty cycle at a subharmonic rate can

suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompensa-

tion of the loop can be used to tame a poor PC layout if

regulatorbandwidthoptimizationisnotrequired.Onlyafter

each controller is checked for its individual performance

should both controllers be turned on at the same time.

A particularly difficult region of operation is when one

controller channel is nearing its current comparator trip

point when the other channel is turning on its top MOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

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