LT6201 datasheet(10/20 Pages) LINER

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LTC2315-12

231512f

For more information www.linear.com/2315-12

tTHROUGHPUT

tACQ-MIN

tACQ-MIN = 40ns

tCONV

tCONV(MIN) = 13 • tSCK + t2 + t10

SCK

SDO

HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B10

B11*

231512 TD06

t10

Figure 6: LTC2315-12 Serial Interface Timing Diagram (SCK High During tACQ)

tTHROUGHPUT = 18 • tSCK

tACQ

tACQ = 4 • tSCK

tCONV

tCONV = 14 • tSCK

SCK

SDO

HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B10

B11*

231512 TD07

t4 t7

t10

Figure 7: LTC2315-12 Serial Interface Timing Diagram (SCK Continuous)

applicaTions inForMaTion

Overview

TheLTC®2315-12isalownoise,highspeed,12-bitsucces-

sive approximation register (SAR) ADC. The LTC2315-12

operates over a wide supply range (2.7V to 5.25V) and

provides a low drift (20ppm/°C maximum), internal refer-

ence and reference buffer. The internal reference buffer is

automatically configured to a 2.048V span in low supply

range (2.7V to 3.6V) and to a 4.096V span in the high

supply range (4.75V to 5.25V). The LTC2315-12 samples

at a 5Msps rate and supports an 87.5MHz data clock. The

LTC2315-12 achieves excellent dynamic performance

(73dB SNR, 84dB THD) while dissipating only 32mW from

a 5V supply at the 5Msps conversion rate.

The LTC2315-12 outputs the conversion data with one

cycle of conversion latency on the SDO pin. The SDO pin

output logic levels are supplied by the dedicated OVDD

supply pin which has a wide supply range (1.71V to 5.25V)

allowingtheLTC2315-12tocommunicatewith1.8V,2.5V,

3V or 5V systems.

TheLTC2315-12providesbothnapandsleeppower-down

modes through serial interface control to reduce power

dissipation during inactive periods.

Serial Interface

TheLT2315-12communicateswithmicrocontrollers,DSPs

and other external circuitry via a 3-wire interface. A falling

CS edge starts a conversion and frames the serial data

transfer.SCKprovidestheconversionclockforthecurrent

sample and controls the data readout on the SDO pin of

the previous sample. CS transitioning low clocks out the

first leading zero and subsequent SCK falling edges clock

out the remaining data as shown in Figures 5, 6 and 7 for

TiMing DiagraMs

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