CT19901 datasheet(10/29 Pages) AEROFLEX

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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700

Pin Description

Signal

Direction

Signal Description

RX DATA 0/1

INPUT

Positive Data In. This should be a TTL description of the positive, half of the

Manchester code data on the bus. It should be driven to a logic level “1” when

a predetermined positive threshold is exceeded on the bus.

RX DATA 0/1

INPUT

Negative Data In. This should be a TTL description of the negative half of the

Manchester code data on the bus. It should be driven to a logic level “1” when

a predetermined negative threshold is exceeded on the bus.

TX INHIBIT 0

OUTPUT

Transmitter Inhibit Bus 0. Normally high. Goes low when the transmitter is

transmitting. Should be used to Inhibit the bus "0" driver.

TX INHIBIT 1

OUTPUT

Transmitter Inhibit Bus 1. Normally high. Goes low when the transmitter is

transmitting. Should be used to Inhibit the bus "1" driver.

TX DATA

OUTPUT

Positive Data Out - When this signal goes high the bus should be driven

positive.

TX DATA

OUTPUT

Negative Data Out - When this signal goes high the bus should be driven

negative.

RTAD 0-4

INPUT

RT address lines - These should be hardwired by the user. RTAD4 is the most

significant bit.

RTADPAR

INPUT

RT address parity line - This must be hardwired by the user to give odd parity.

BIT DECODE

INPUT

Built-ln Test Decode - When held low, prevents resetting TXTO Bit, HSFAIL

Bit, and LTFAIL Bit in the BIT Word (as well as TF and SSF Bits in the Status

Word) upon receipt of a Transmit Bit Word Mode Command.

BCSTEN 0/1

INPUT

Broadcast command enable Bus 0/1 - When low the recognition of

broadcast command is prevented on both Bus 0 and 1. CT1991 only.

BCSTEN 0

INPUT

Broadcast command enable Bus 0 - When low the recognition of broadcast

command is prevented on Bus 0. CT1990 only.

BCSTEN 1

INPUT

Broadcast command enable Bus 1 - When low the recognition of broadcast

command is prevented on Bus 1. CT1990 only.

6MCK

INPUT

6 Megahertz master clock.

IH 08 (LSB)

IH 19

IH 210

IH 311

IH 412

IH 513

IH614

IH715 (MSB)

BI-DIRECTIONAL

Internal Highway - Bi-directional 8 bit highway on which 16 bit words are

passed in two bytes. IH 715 is the most significant bit of each byte, the most

significant byte being transferred first. The highway should only be driven by

the subsystem when data is to be transferred to the RT.

DTRQ

OUTPUT

Data Transfer Request - Goes low to request a data transfer between the

ASIC and subsystem. Goes high at the end of the transfer.

DTAK

INPUT

Data Transfer Acknowledge - Goes low to indicate that the subsystem is

ready for the data transfer.

IUSTB

OUTPUT

Interface Unit Strobe - This is a double pulse strobe used to transfer the two

bytes of data

H/L

OUTPUT

High/Low - Indicates which byte of data is on the internal highway. Logic level

"0" for least significant byte.

GBR

OUTPUT

Good Block Received - Pulses low for 500ns when a block of data has been

received by the ASIC and has passed all the validity and error checks.

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