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OR3LP26B Datasheet(PDF) 109 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 109 Page - Agere Systems |
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109 / 184 page  Lucent Technologies Inc. 109 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. PCI Bus Core Detailed Description Quad Port (continued) 5-8844(F).a Figure 38. Target Write Memory 32-Byte Burst (FPGA Bus, Quad-Port, 32-Bit Address) Table 39. Quad-Port Target Write * treqn is deasserted high on the last data DWORD. † twlastcycn is asserted low on the last data DWORD. tstatecntr Next State of tstatecntr Description Bus treqn twlastcycn taenn 0 0 Idle — 111 0 1 or 4 Address[31:0] twdata[35:0] 0 1 0 1 4 Address[63:32] twdata[32:0] 0 0 0 4 5 or 0 Data[31:0], BE[3:0] twdata[35:0] 0 1 1 5 4 or 0 Data[63:32], BE[7:4] twdata[35:0] 1† 0* 1 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 0 4 5 4 5 4 5 4 5 0 X CMD X X ADRS D0 D1 D2 D3 D4 D5 D6 D7 X fclk t_ready treqn tstatecntr tcmd twdata taenn twdataenn twlastcycn tw_emptyn tw_aemptyn |
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