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OR3LP26B Datasheet(PDF) 123 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 123 Page - Agere Systems |
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123 / 184 page  Lucent Technologies Inc. 123 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. Configuration Space of the PCI Core The following section describes the configuration space of the PCI core. This includes the layout and organization as called out in the PCI Specification as well as details specific to the PCI core’s implementation. Note that the term configuration has two meanings: in the FPGA context, it refers to the programming of the FPGA’s SRAM to define its functionality, and in the PCI context, it refers to the process of initializing the personality of the PCI agent residing at a specific location or card slot via a data space that is physically addressed. The PCI’s configuration space is being discussed here. PCI Bus Configuration Space Organization Table 41 shows the layout of the PCI core’s configuration space. The header type is 00 hex (non-PCI-to-PCI bridge). All required and many optional features are implemented. Note that the defined space extends beyond 3F hex, and includes provisions for hot swap and FPGA configuration via the PCI bus. Table 42 further details the con- tent and function of each register in the PCI configuration space. Table 41. Configuration Space Layout 31 16 15 0 Device ID Vendor ID 00h Status Command 04h Class Code Revision ID 08h BIST Header Type Latency Timer Cache Line Size 0Ch Base Address Registers 10h 14h 18h 1Ch 20h 24h Cardbus CIS Pointer 28h Subsystem ID Subsystem Vendor ID 2Ch Expansion ROM Base Address 30h Reserved Cap_Ptr 34h Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch Reserved FPGA Configuration Command-Status Register 40h FPGA Configuration Data Register 44h Scratch Register 48c Reserved 40c Reserved HS_CSR Next Item Capability ID 48h Reserved 54h thru FFh |
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