OR3LP26B datasheet(127/184 Pages) AGERE

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Lucent Technologies Inc.

127

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

FPSC Configuration (continued)

Write a DWORD of FPSC configuration data to

FCDR. This will set pciregvld in the FCCSR to

active-high, indicating that it holds a valid DWORD

of data. The user should always continue to moni-

tor initn and Done.

10. Read the FCCSR until pciregvld goes inactive-

low, and srempty goes high indicating that the

DWORD it contained has been transferred to the

shift register that feeds the serial configuration data

to the FPSC. The user should always continue to

monitor initn and Done.

11. Repeat steps 9 and 10 until all the configuration

data has been written. The user should always

continue to monitor initn and Done.

12. Read the FCCSR and verify that Done went active-

high, indicating that the configuration was success-

ful.

13. Write configFPGA low.

Readback via PCI interface

The procedure for performing a readback via the PCI

interface is similar to the above procedure for configur-

ing, and also similar to the standard readback proce-

dure. The steps are outlined below:

1. Read the FCCSR until bit 0 goes high. If communi-

cation with the FPSC is underway via the boundary-

scan hardware, this signal will remain inactive-low

until it completes.

2. Write to the FCCSR with rdcfgn active-low. This

enables the readback mode.

3. Read the FCCSR until sregfull goes active-high,

indicating that a DWORD of data is available in reg-

ister FCDR.

4. Read the data from the FCDR.

5. Repeat steps 3 and 4 until all readback data has

been accessed.

6. Write RdCfgN high.

7. Write ConfigFPGA high (no pulse on prgmn)

8. Write all 1s to FCDR

9. Loop on FCCSR until srempty goes high and pcir-

egvld goes low.

10.Write CongfigFPGA low.

Interaction Among Configuration Modes

The basic configuration options, including configuration

via the microprocessor and boundary-scan interfaces,

are performed in a manner identical to that of

ORCA

Series 3 FPGAs. FPSC configuration via the PCI inter-

face is available at any time, either prior to or after the

FPSC has been configured and regardless of the value

to which the FPGA configuration mode pins (M2, M1,

and M0) have been strapped. In addition, a PCI-

directed configuration will override any strapped config-

uration operation already underway, an FPGA configu-

ration via the boundary-scan interface will override one

via the PCI interface, and the PRGM pin overrides

both.

OR3LP26B Datasheet(PDF) 127 Page - Agere Systems

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