OR3LP26B datasheet(130/184 Pages) AGERE

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Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

FPGA Configuration Data Format

The

ORCA Foundry development system interfaces

with front-end design entry tools and provides tools to

produce a fully configured FPSC. This section dis-

cusses using the

ORCA Foundry development system

to generate configuration RAM data and then provides

the details of the configuration frame format.

Using

ORCA Foundry to Generate

Configuration RAM Data

The configuration data bit stream defines the PCI

embedded core configuration, the FPGA logic function-

ality, and the I/O configuration and interconnection. The

data bit stream is generated by the

ORCA Foundry

development tools. The bit stream created by the bit

stream generation tool is a series of 1s and 0s used to

write the FPSC configuration RAM. It can be loaded

into the FPSC using one of the configuration modes

discussed elsewhere in this data sheet.

For FPSCs, the bit stream is prepared in two separate

steps in the design flow. The configuration options of

the embedded core are specified using

ORCA

OR3LP26B Design Kit Software at the beginning of the

design process. This offers the designer a specific con-

figuration to simulate and design the FPGA logic to.

Upon completion of the design, the bit stream genera-

tor combines the embedded core options and the

FPGA configuration into a single bit stream for down-

load into the FPSC.

FPGA Configuration Data Frame

Configuration data can be presented to the FPSC in

two frame formats: autoincrement and explicit. A

detailed description of the frame formats is shown in

Figure 49, Figure 50, and Table 43. The two modes are

similar except that autoincrement mode uses assumed

address incrementation to reduce the bit stream size,

and explicit mode requires an address for each data

frame. In both cases, the header frame begins with a

series of 1s and a preamble of 0010, followed by a

24-bit length count field representing the total number

of configuration clocks needed to complete the loading

of the FPSC.

The mandatory ID frame contains data used to deter-

mine if the bit stream is being loaded to the correct type

ORCA device (i.e., a bit stream generated for an

OR3LP26B is being sent to an OR3LP26B). Error

checking is always enabled for Series 3+ devices,

through the use of an 8-bit checksum. One bit in the ID

frame also selects between the autoincrement and

explicit address modes for this load of the configuration

data.

A configuration data frame follows the ID frame. A data

frame starts with a one-start bit pair and ends with

enough one-stop bits to reach a byte boundary. If using

autoincrement configuration mode, subsequent data

frames can follow. If using explicit mode, one or more

address frames must follow each data frame, telling the

FPSC at what addresses the preceding data frame is to

be stored (each data frame can be sent to multiple

addresses).

Following all data and address frames is the postam-

ble. The format of the postamble is the same as an

address frame with the highest possible address value

with the checksum set to all ones.

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