OR3LP26B datasheet(132/184 Pages) AGERE

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132

Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

FPGA Configuration Data Format

(continued)

The length and number of data frames and information

on the PROM size for the OR3LP26B is given in Table

44.

Table 44. Configuration Frame Size

Bit Stream Error Checking

There are three different types of bit stream error

checking performed in the

ORCA Series 3+ FPSCs:

ID frame, frame alignment, and CRC checking.

The ID data frame is sent to a dedicated location in the

FPSC. This ID frame contains a unique code for the

device for which it was generated. This device code is

compared to the internal code of the FPSC. Any differ-

ences are flagged as an ID error. This frame is auto-

matically created by the bit stream generation program

ORCA Foundry.

Each data and address frame in the FPSC begins with

a frame start pair of bits and ends with eight stop bits

set to 1. If any of the previous stop bits were a 0 when a

frame start pair is encountered, it is flagged as a frame

alignment error.

Error checking is also done on the FPSC for each

frame by means of a checksum byte. If an error is found

on evaluation of the checksum byte, then a

checksum/parity error is flagged.

When any of the three possible errors occur, the FPSC

is forced into an idle state, forcing INIT low. The FPSC

will remain in this state until either the RESET or PRGM

pins are asserted.

If using either of the MPI modes or the PCI embedded

core to configure the FPSC, the specific type of bit

stream error is written to one of the MPI registers or a

PCI register, respectively, by the FPGA configuration

logic. The PGRM bit of the MPI control register or the

PCI embedded core can also be used to reset out of

the error condition and restart configuration.

FPGA Configuration Modes

There are eight methods for configuring the FPSC. Six

of the configuration modes are selected on the M0, M1,

and M2 input and are shown in Table 45. The seventh

mode is PCI bus configuration as previously discussed

and the eighth configuration mode is accessed through

the boundary-scan interface. A fourth input, M3, is

used to select the frequency of the internal oscillator,

which is the source for CCLK in some configuration

modes. The nominal frequencies of the internal oscilla-

tor are 1.25 MHz and 10 MHz. The 1.25 MHz fre-

quency is selected when the M3 input is unconnected

or driven to a high state.

Note that the Master parallel mode of configuration that

is available in the

ORCA Series 3 FPGAs is not avail-

able in the OR3LP26B. This is due to the use of Master

parallel configuration pins for the PCI bus interface.

More information on the general FPGA modes of con-

figuration can be found in the

ORCA Series 3 data

sheet.

Table 45. Configuration Modes

Motorola is a registered trademark of Motorola, Inc.

†

Intel is a registered trademark of Intel Corporation.

Devices

OR3LP26B

n of Frames

1880

Data Bits/Frame

292

Configuration Data (# of frames • # of

data bits/frame)

548,960

Maximum Total # Bits/Frame (align

bits, 01 frame start, 8-bit checksum,

eight stop bits)

312

Maximum Configuration Data

(# bits/frame • # of frames)

586,560

Maximum PROM Size (bits)

(add configuration header and postam-

ble)

586,728

CCLK

Configuration

Mode

Data

Output

Master Serial

Serial

Input

Slave Parallel

Parallel

Output

Microprocessor:

Motorola* Pow-

erPC

Parallel

Output

Microprocessor:

Intel

† i960

Parallel

100

Reserved

101

Output

Async Peripheral

Parallel

110

Reserved

Input

Slave Serial

Serial

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