OR3LP26B datasheet(139/184 Pages) AGERE

139 / 184 page

Lucent Technologies Inc.

139

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 54. OR3LP26B Fast Clock (fclk) to Output Delay (Pin-to-Pin)

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

Timing is without the use of the programmable clock manager (PCM).

This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the

PIO CLK input, the clock

→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not

used. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used.

5-4846(F).b

Figure 52. Fast Clock to Output Delay

Description

(TJ = 85 °C, VDD = min)

Min

Max

Unit

Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)

ECLK Middle Input Pin

→OUTPUT Pin (Fast)

—9.06

ECLK Middle Input Pin

→OUTPUT Pin (Slewlim)

—9.86

ECLK Middle Input Pin

→OUTPUT Pin (Sinklim)

—

14.3

Additional Delay if ECLK Corner Pin Used

—

2.2

OUTPUT (50 pF LOAD)

ECLK

fclk

PIO FF

CLKCNTRL

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