OR3LP26B datasheet(143/184 Pages) AGERE

143 / 184 page

Lucent Technologies Inc.

143

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 58. OR3LP26B Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

The pin-to-pin timing parameters in this table should be used instead of results reported by

ORCA Foundry.

This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer delay and the clock routing to the PIO

FF CLK input. The delay will be reduced if any of the clock branches are not used. The given setup (delayed and no delay) and hold (delayed)

timing allows the input clock pin to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing

assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF is used. If the clock pin is located

elsewhere, then the last parameter in the table must be added to the hold (no delay) timing.

5-4847(F)

Figure 56. Input to System Clock Setup/Hold Time

Table 59. OR3LP26B PCI and FPGA Interface Clock Operation Frequencies

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

* The PCI clock frequency is based on the internal register to register frequency and the 66 MHz PCI I/O specifications.

† The maximum user interface clock frequencies are values based on registering all signals at the FPGA/ASIC boundary. This number will be

lower depending on the design implementation and number of FPGA logic levels into and out of the ASIC.

‡ This is the typical operating frequency for a real design that does not register signals at the FPGA/ASIC boundary.

Description (TJ = 85 °C, VDD = min)

Min

Max

Unit

Input to SCLK Setup Time

0.0

—

Input to SCLK Setup Time (delayed data input)

5.02

—

Input to SCLK Hold Time

5.47

—

Input to SCLK Hold Time (delayed data input)

0.0

—

Additional Hold Time if Non-mid-PIC Used as SCLK Pin (no

delay on data input)

0.83

—

Description (TI = 85 °C, VDD = min, VDD2 = min)

Speed

–8

Unit

Signal

Min

Typ

Max

Clk (PCI clock)

66*

MHz

Fclk1 (user interface clock)

66†

100‡

MHz

Fclk2 (user interface clock)

66†

100‡

MHz

SCLK

INPUT

PIO FF

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