OR3LP26B datasheet(145/184 Pages) AGERE

145 / 184 page

Lucent Technologies Inc.

145

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 62. OR3LP26B Interbuf Delays

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Note: The interbufs are buffers that interface between the FPGA and the ASIC.

Table 63. OR3LP26B FPGA Side Interface Clock to Output Delays, pciclk Synchronous Signals

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Note: The clock to out parameters are measured from the pciclk clock output pin on the FPGA side, excluding the interbufs, which traverse the

ASIC/FPGA boundary. The

ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the clock and data

paths.

Description (TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

Interbuf from FPGA to ASIC

—

0.592

Interbuf from ASIC to FPGA

—

0.429

Description (TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

mw_emptyn

—

4.985

mr_fulln

—

4.458

tr_emptyn

—

4.686

tw_fulln

—

4.703

tcmd[3:0]

—

4.345

bar[2:0]

—

4.139

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