OR3LP26B datasheet(146/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

146

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 64. OR3LP26B FPGA Side Interface Clock to Output Delays, fclk Synchronous Signals

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Note: The clock to out parameters are measured from the FCLK1 and FCLK2 clock input pins on the FPGA side, excluding the interbufs, which

traverse the ASIC/FPGA boundary. The

ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the

clock and data paths.

Description (TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

fpga_msyserror

—

3.779

pci_mcfg_stat

—

4.404

ma_fulln

—

4.314

mstatecntr[2:0]

—

5.796

m_ready

—

4.758

mw_fulln

—

4.348

mw_afulln

—

3.734

datatofpga[63:0] (dual-port mode)

—

8.679

datatofpgax[7:0] (dual-port mode)

—

7.974

mrdata[35:0] (quad-port mode)

—

8.479

twdata[35:0] (quad-port mode)

—

6.867

mr_emptyn

—

3.840

mr_aemptyn

—

3.684

mrlastcycn

—

7.536

disctimerexpn

—

3.436

pci_tcfg_stat

—

3.777

treqn

—

4.932

t_ready

—

4.817

tstatecntr[2:0]

—

4.355

tw_emptyn

—

3.893

tw_aemptyn

—

3.759

twlastcycn

—

7.557

tr_fulln

—

4.358

tr_afulln

—

3.915

trlastcycn

—

5.533

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