T7121-PL2 datasheet(39/68 Pages) AGERE

39 / 68 page

Lucent Technologies Inc.

Data Sheet

April 1997

T7121 HDLC Interface for ISDN (HIFI-64)

Functional Description (continued)

Table 18. Register R11—Receiver Time-Slot Offset Control Register

R11—B7

R11—B6

R11—B5

R11—B4

R11—B3

R11—B2

R11—B1

R11—B0

DRI

(0)

RLBIT

(1)

RTSOF5

(0)

RTSOF4

(0)

RTSOF3

(0)

RTSOF2

(0)

RTSOF1

(0)

RTSOF0

(0)

Bit

Symbol

Name/Function

R11

B(0—5)

RTSOF0—RTSOF5 Receiver Time-Slot Offset. The value of these 6 bits, coded in

binary with bit 0 being the LSB, speciﬁes the number of time slots

to delay between the beginning of the ﬁrst locatable TDM highway

time slot and the beginning of a new virtual TDM frame (i.e., the

time slot deﬁned by the user as time slot 0.) See Figure 5 for an

example of using the RTSOF bits.

R11

RLBIT

Receive Least Signiﬁcant Bit First. This bit is used to control

whether the least signiﬁcant or most signiﬁcant data bit is

received ﬁrst. The least signiﬁcant data bit in the receive FIFO is

deﬁned as that bit which is read on AD0 when the FIFO is read.

When RLBIT is 0, the most signiﬁcant bit of data is received ﬁrst,

and when RLBIT is set to 1, the least signiﬁcant bit of data is

received ﬁrst.

RLBIT has no meaning when not in the TDM highway mode (i.e.,

HWYEN, R0—B7 = 0). In non-TDM highway mode, data is

always received least signiﬁcant bit ﬁrst.

R11

DRI

Receive Data Inverted. If this bit is set to 1, the serial data input

to the DRA (or DRB) pin is inverted before data is passed to the

HDLC receiver (or FIFO in the transparent mode).

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