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T7121-PL2 Datasheet(PDF) 49 Page - Agere Systems |
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T7121-PL2 Datasheet(HTML) 49 Page - Agere Systems |
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49 / 68 page ![]() Lucent Technologies Inc. 49 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Timing Characteristics (continued) 5-5043 Figure 17. FE = 1, CLKXI = 0, CLKRI = 0 5-5044 Figure 18. FE = 1, CLKXI = 1, CLKRI = 0 0 1 234567 0 1 234567 FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR FIRST BIT TRANSMITTED CLKX/CLKR FS (FE = 1) DXA/B (CLKXI = 0) TSCA DRA/B (CLKRI = 0) 3-STATE FIRST BIT SAMPLED DON'T CARE 0 1 234567 0 1 234567 FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR FIRST BIT TRANSMITTED CLKX/CLKR FS (FE = 1) DXA/B (CLKXI = 1) TSCA DRA/B (CLKRI = 0) 3-STATE FIRST BIT SAMPLED DON'T CARE |
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