MPC932

TIMING SOLUTIONS

BR1333 — REV 5

5

MOTOROLA

Power Supply Filtering

The MPC932 is a mixed analog/digital product and as

such it exhibits some sensitivities that would not necessarily

be seen on a fully digital product. Analog circuitry is naturally

susceptible to random noise, especially if this noise is seen

on the power supply pins. The MPC932 provides separate

power supplies for the output buffers (VCCO) and the internal

PLL (VCCA) of the device. The purpose of this design

technique is to try and isolate the high switching noise digital

outputs from the relatively sensitive internal analog

phase–locked loop. In a controlled environment such as an

evaluation board this level of isolation is sufficient. However,

in a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of

isolation may be required. The simplest form of isolation is a

power supply filter on the VCCA pin for the MPC932.

Figure 3. Power Supply Filter

VCCA

VCC

MPC932

0.01

µF

22

µF

0.01

µF

3.3V

RS=10–15Ω

Figure 3 illustrates a typical power supply filter scheme.

The MPC932 is most susceptible to noise with spectral

content in the 1KHz to 1MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop that will be seen between the VCC supply and the VCCA

pin of the MPC932. From the data sheet the IVCCA current

(the current sourced through the VCCA pin) is typically 15mA

(20mA maximum), assuming that a minimum of 3.0V must be

maintained on the VCCA pin very little DC voltage drop can

be tolerated when a 3.3V VCC supply is used. The resistor

shown in Figure 3 must have a resistance of 10–15

Ω to meet

the voltage drop criteria. The RC filter pictured will provide a

broadband filter with approximately 100:1 attenuation for

noise whose spectral content is above 20KHz. As the noise

frequency crosses the series resonant point of an individual

capacitor it’s overall impedance begins to look inductive and

thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance

path to ground exists for frequencies well above the

bandwidth of the PLL.

Although the MPC932 has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may

be applications in which overall performance is being

degraded due to system power supply noise. The power

supply filter schemes discussed in this section should be

adequate to eliminate power supply noise related problems

in most designs.

Driving Transmission Lines

The MPC932 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 10

Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091 in the

Timing Solutions brochure (BR1333/D).

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a

point–to–point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50

Ω resistance to VCC/2. This technique draws a fairly high

level of DC current and thus only a single terminated line can

be driven by each output of the MPC932 clock driver. For the

series terminated case however there is no DC current draw,

thus the outputs can drive multiple series terminated lines.

Figure 4 illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC932 clock

driver is effectively doubled due to its capability to drive

multiple lines.

Figure 4. Single versus Dual Transmission Lines

7

Ω

IN

MPC932

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutA

7

Ω

IN

MPC932

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutB0

RS = 43Ω

ZO = 50Ω

OutB1

The waveform plots of Figure 5 show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC932 output buffers is

more than sufficient to drive 50

Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations a delta of only 43ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output–to–output skew of the MPC932. The output waveform

in Figure 5 shows a step in the waveform, this step is caused

by the impedance mismatch seen looking into the driver. The

parallel combination of the 43

Ω series resistor plus the output

impedance does not match the parallel combination of the