LSM330DLCTR datasheet(49/66 Pages) STMICROELECTRONICS

49 / 66 page

LSM330DLC

Doc ID 022162 Rev 2

49/66

Interrupt 1 source register. Read only register.

Reading at this address clears INT1_SRC_A IA bit (and the interrupt signal on INT 1 pin)

and allows the refreshing of the data in the INT1_SRC_A register if the latched option was

chosen.

8.16

INT1_THS_A (32h)

8.17

INT1_DURATION_A (33h)

D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration

steps and maximum values depend on the ODR chosen.

Y high. Default value: 0

(0: no interrupt, 1: Y High event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y Low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X High event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X Low event has occurred)

Table 46.

INT1_SRC_A description (continued)

Table 47.

INT1_THS_A register

0(1)

This bit has to be set ‘0’ for correct operation.

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 48.

INT1_THS_A description

THS6 - THS0

Interrupt 1 threshold. Default value: 000 0000

Table 49.

INT1_DURATION_Aregister

0(1)

This bit must be set ‘0’ for correct operation.

Table 50.

INT1_DURATION_A description

D6 - D0

Duration value. Default value: 000 0000

LSM330DLCTR Datasheet(PDF) 49 Page - STMicroelectronics

LSM330DLCTR Datasheet(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL