Block Diagram

2

Pin Configuration & Marking Information

A:

Pin Configuration

Y:

Year

W: Week

X:

Internal Code

,

Power Analog Microelectronics Inc

www.poweranalog.com

Name

Pin Num ber

Function

PGND

1 - 3

Main power ground pin

FB

4

Feedback voltage to internal error amplifier, the threshold voltage is 0.6V.

GND

5

Signal ground for small signal components.

NC

6, 16

No connection

EN

7

Enable control input. Force this pin voltage above 1.5V, enables the chip, and

below 0.3V s huts down t he dev ice.

TEST

8

Test Mode(no connect or to Ground)

VIN

9

Bias supply. Chip main power supply pin

PVIN

10 -12

Input supply for power s tage. Must be c losely decoupled to PGND

SW

13 -15

The drains of the internal main and synchronous power MOS FET.

Pin Description

Top View

12

11

10

9

13

14

15

16

1

2

3

4

8

7

6

5

FB

PGND

PGND

PGND

PVIN

PVIN

VIN

PVIN

P2307A

XXXYW

EN

R1

R2

FB

+

-

IAMP

+

-

IRCMP

SW

PGND

SYNCHRONOUS

RECTIFIER NCH

(

)

MAIN

SWITCH PCH

(

)

PVIN

COMP

VIN

SHUTDOWN

OSC

RS LATCH

0.6VREF

FREQ

SHIFT

-

+

EA

S Q

R Q

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

SLOPE

COMP

1.5M

OSC

ANTI

SHOOT

THRU

-

-

TEST

VIN

GND

PAM2307

3A Low Noise Step-Down DC-DC Converter

QFN 3X3 16L

03/2011 Rev2.1