EVAL-AD7705EB datasheet(28/44 Pages) AD

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AD7705/AD7706

Rev. C | Page 28 of 44

THEORY OF OPERATION

CLOCKING AND OSCILLATOR CIRCUIT

The AD7705/AD7706 each require a master clock input, which

can be an external CMOS-compatible clock signal applied to

the MCLK IN pin with the MCLK OUT pin left unconnected.

Alternatively, a crystal or ceramic resonator of the correct

frequency can be connected between MCLK IN and

MCLK OUT, as shown in Figure 17. In this case, the clock

circuit functions as an oscillator, providing the clock source for

the part. The input sampling frequency, modulator sampling

frequency, –3 dB frequency, output update rate, and calibration

time are directly related to the master clock frequency, fCLKIN.

Reducing the master clock frequency by a factor of two halves

the above frequencies and update rate and doubles the

calibration time. The current drawn from the VDD power supply

is also related to fCLKIN. Reducing fCLKIN by a factor of two halves

the digital part of the total VDD current, but does not affect the

current drawn by the analog circuitry.

MCLK IN

MCLK OUT

CRYSTAL OR

CERAMIC

RESONATOR

AD7705/AD7706

Figure 17. Crystal/Resonator Connection for the AD7705/AD7706

Using the part with a crystal or ceramic resonator between the

MCLK IN pin and MCLK OUT pin generally causes more

current to be drawn from VDD than does clocking the part from

a driven clock signal at the MCLK IN pin. This is because the

on-chip oscillator circuit is active in the case of the crystal or

ceramic resonator. Therefore, the lowest possible current on the

AD7705/AD7706 is achieved with an externally applied clock at

the MCLK IN pin with MCLK OUT unconnected, unloaded, and

disabled.

The amount of additional current taken by the oscillator

depends on a number of factors. For example, the larger the

value of the capacitor (C1 and C2) placed on the MCLK IN and

MCLK OUT pins, the larger the current consumption on the

AD7705/AD7706. To avoid unnecessarily consuming current,

care should be taken not to exceed the capacitor values

recommended by the crystal and ceramic resonator manufac-

turers. Typical values for C1 and C2 are recommended by

crystal or ceramic resonator manufacturers, usually in the range

of 30 pF to 50 pF. If the capacitor values on MCLK IN and

MCLK OUT are kept in this range, they do not result in any

excessive current. Another factor that influences the current is

the effective series resistance (ESR) of the crystal that appears

between the MCLK IN and MCLK OUT pins of the AD7705/

AD7706. As a general rule, the lower the ESR value, the lower

the current taken by the oscillator circuit.

When operating with a clock frequency of 2.4576 MHz, there is

a 50 μA difference in the current between an externally applied

clock and a crystal resonator operated with a VDD of 3 V. With

VDD = 5 V and fCLKIN = 2.4576 MHz, the typical current increases

by 250 μA for a crystal- or resonator-supplied clock vs. an

externally applied clock. The ESR values for crystals and

resonators at this frequency tend to be low, and, as a result,

there tends to be little difference between different crystal and

resonator types.

When operating with a clock frequency of 1 MHz, the ESR

value for different crystal types varies significantly. As a result,

the current drain varies across crystal types. When using a crystal

with an ESR of 700 Ω, or when using a ceramic resonator, the

increase in the typical current over an externally applied clock is

20 μA with VDD = 3 V, and 200 μA with VDD = 5 V. When using

a crystal with an ESR of 3 kΩ, the increase in the typical current

over an externally applied clock is 100 μA with VDD = 3 V, but

400 μA with VDD = 5 V.

There is a start-up time before the on-chip oscillator circuit

oscillates at its correct frequency and voltage levels. Typical start-

up times with VDD = 5 V are 6 ms using a 4.9512 MHz crystal,

16 ms with a 2.4576 MHz crystal, and 20 ms with a 1 MHz crystal

oscillator. Start-up times are typically 20% slower when a 3 V

power supply is used. With 3 V supplies, depending on the loading

capacitances on the MCLK pins, a 1 MΩ feedback resistor might

be required across the crystal or resonator to keep the start-up

times around 20 ms.

The AD7705/AD7706 master clock appears on the MCLK OUT

pin of the device. The maximum recommended load on this pin

is 1 CMOS load. When using a crystal or ceramic resonator to

generate the AD7705/AD7706 clock, it might be desirable to

use this clock as the clock source for the system. In this case, it

is recommended that the MCLK OUT signal be buffered with a

CMOS buffer before being applied to the rest of the circuit.

SYSTEM SYNCHRONIZATION

The FSYNC bit of the setup register allows the user to reset the

modulator and digital filter without affecting the setup conditions

on the part. This allows the user to start gathering samples of the

analog input at a known point in time, that is, when the FSYNC

changes from 1 to 0.

With a 1 in the FSYNC bit of the setup register, the digital filter

and analog modulator are held in a known reset state, and the

part does not process input samples. When a 0 is written to the

FSYNC bit, the modulator and filter are taken out of this reset

state, and the part resumes gathering samples on the next

master clock edge.

EVAL-AD7705EB Datasheet(PDF) 28 Page - Analog Devices

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