EVAL-AD7705EB datasheet(22/44 Pages) AD

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AD7705/AD7706

Rev. C | Page 22 of 44

ANALOG INPUT

Ranges

The AD7705 contains two differential analog input pairs,

AIN1(+)/AIN1(−) and AIN2(+)/AIN2(−). These input pairs

provide programmable-gain, differential input channels that can

handle either unipolar or bipolar input signals. It should be noted

that the bipolar input signals are referenced to the respective

AIN(−) input of each input pair. The AD7706 contains three

pseudo differential analog input pairs, AIN1, AIN2, and AIN3,

which are referenced to the COMMON input.

In unbuffered mode, the common-mode range of the input is

from GND to VDD, provided that the absolute value of the analog

input voltage lies between GND − 100 mV and VDD + 30 mV.

Therefore, in unbuffered mode, the part can handle both unipolar

and bipolar input ranges for all gains. The AD7705 can tolerate

absolute analog input voltages down to GND − 200 mV, but the

leakage current increases at high temperatures. In buffered mode,

the analog inputs can handle much larger source impedances,

but the absolute input voltage range is restricted to between

GND + 50 mV and VDD − 1.5 V, which also restricts the common-

mode range. Therefore, in buffered mode, there are some

restrictions on the allowable gains for bipolar input ranges. Care

must be taken in setting up the common-mode voltage and

input voltage ranges so that the above limits are not exceeded;

otherwise, there is a degradation in linearity performance.

In unbuffered mode, the analog inputs look directly into the

7 pF input sampling capacitor, CSAMP. The dc input leakage

current in this unbuffered mode is 1 nA maximum. As a result,

the analog inputs see a dynamic load that is switched at the

input sample rate (see Figure 14). This sample rate depends on

master clock frequency and selected gain. CSAMP is charged to

AIN(+) and discharged to AIN(−) every input sample cycle.

The effective on resistance of the switch, RSW, is typically 7 kΩ.

CSAMP must be charged through RSW and any external source

impedances every input sample cycle. Therefore, in unbuffered

mode, source impedances mean a longer charge time for CSAMP,

which might result in gain errors on the parts. Table 22 shows

the allowable external resistance-capacitance values for unbuffered

mode, such that no gain error to the 16-bit level is introduced in

the part. Note that these capacitances are total capacitances on

the analog input—external capacitance plus 10 pF capacitance

from the pins and lead frame of the devices.

AIN(+)

AIN(–)

SWITCHING FREQUENCY DEPENDS ON

fCLKIN AND SELECTED GAIN

RSW (7kΩ TYP)

CSAMP

(7pF)

HIGH

IMPEDANCE

>1G

VBIAS

Figure 14. Unbuffered Analog Input Structure

Table 22. External Resistance-Capacitance Combination for

Unbuffered Mode (Without 16-Bit Gain Error)

External Capacitance (pF)

Gain

100

500

1000

5000

152 kΩ

53.9 kΩ

31.4 kΩ

8.4 kΩ

4.76 kΩ

1.36 kΩ

75.1 kΩ

26.6 kΩ

15.4 kΩ

4.14 kΩ

2.36 kΩ

670 Ω

34.2 kΩ

12.77 kΩ

7.3 kΩ

1.95 kΩ

1.15 kΩ

320 Ω

8 to 128

16.7 kΩ

5.95 kΩ

3.46 kΩ

924 Ω

526 Ω

150 Ω

In buffered mode, the analog inputs look into the high impedance

inputs stage of the on-chip buffer amplifier. CSAMP is charged via

this buffer amplifier such that source impedances do not affect

the charging of CSAMP. This buffer amplifier has an offset leakage

current of 1 nA. In this buffered mode, large source impedances

result in a small dc offset voltage developed across the source

impedance, but not in a gain error.

Sample Rate

The modulator sample frequency for the AD7705/AD7706

remains at fCLKIN/128 (19.2 kHz @ fCLKIN = 2.4576 MHz), regardless

of the selected gain. However, gains greater than 1 are achieved

by a combination of multiple input samples per modulator cycle

and a scaling of the ratio of reference capacitor to input capacitor.

As a result of the multiple sampling, the input sample rate of

these devices varies with the selected gain (see Table 23). In

buffered mode, the input is buffered before the input sampling

capacitor. In unbuffered mode, where the analog input looks

directly into the sampling capacitor, the effective input impedance

is 1/CSAMP × fS, where CSAMP is the input sampling capacitance

and fS is the input sample rate.

Table 23. Input Sampling Frequency vs. Gain

Gain

Input Sampling Frequency (fS)

fCLKIN/64 (38.4 kHz @ fCLKIN = 2.4576 MHz)

2 × fCLKIN/64 (76.8 kHz @ fCLKIN = 2.4576 MHz)

4 × fCLKIN/64 (76.8 kHz @ fCLKIN = 2.4576 MHz)

8 to 128

8 × fCLKIN/64 (307.2 kHz @ fCLKIN = 2.4576 MHz)

BIPOLAR/UNIPOLAR INPUT

The analog inputs on the AD7705/AD7706 can accept either

unipolar or bipolar input voltage ranges. Bipolar input ranges

do not imply that these parts can handle negative voltages on

their analog inputs; the analog inputs cannot go more negative

than −100 mV to ensure correct operation of these parts. The

input channels are fully differential. As a result, on the AD7705,

the voltage to which the unipolar and bipolar signals on the

AIN(+) input are referenced is the voltage on the respective

AIN(−) input.

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