EVAL-AD7705EB datasheet(26/44 Pages) AD

26 / 44 page

AD7705/AD7706

Rev. C | Page 26 of 44

For a full system calibration, the zero-scale point must be

presented to the converter first. It must be applied to the

converter before the calibration step is initiated and remain

stable until the step is complete. Once the zero-scale voltage is

set up, a zero-scale system calibration is initiated by writing the

appropriate values (1, 0) to the MD1 and MD0 bits of the setup

selected gain. The duration of the calibration is 3 × 1/output

rate. Then, Bit MD1 and Bit MD0 in the setup register return to

0, 0, providing the earliest indication that the calibration

sequence is complete. The DRDY line goes high when calibration

is initiated and returns low when there is a valid new word in the

data register. The duration time from the calibration command

being issued to DRDY going low is 4 × 1/output rate, because

the part performs a normal conversion on the AIN voltage before

DRDY goes low.

If DRDY is low before (or goes low during) writing the

calibration command to the setup register, it can take up to one

modulator cycle (MCLK IN/128) before DRDY goes high to

indicate that a calibration is in progress. Therefore, DRDY

should be ignored for one modulator cycle after the last bit is

written to the setup register in the calibration command.

After the zero-scale point is calibrated, the full-scale point is

applied to AIN, and the second step of the calibration process is

initiated by writing the appropriate values (1, 1) to MD1 and

MD0. The full-scale voltage must be set up before the calibration

is initiated and must remain stable throughout the calibration

step. The full-scale system calibration is performed at the

selected gain. The duration of the calibration is 3 × 1/output

rate. Then, the MD1 and MD0 bits in the setup register return

to 0, 0, providing the earliest indication that the calibration

sequence is complete. The DRDY line goes high when calibration

is initiated and returns low when there is a valid new word in

the data register. The duration time from the calibration

command being issued to DRDY going low is 4 × 1/output rate,

because the part performs a normal conversion on the AIN

voltage before DRDY goes low. If DRDY is low before (or goes

low during) writing the calibration command to the setup

before DRDY goes high to indicate that calibration is in

progress. Therefore, DRDY should be ignored for one

modulator cycle after the last bit is written to the setup register

in the calibration command.

In unipolar mode, the system calibration is performed between

the two endpoints of the transfer function. In bipolar mode, it is

performed between midscale (zero differential voltage) and

positive full scale.

The fact that the system calibration involves two steps offers

another feature. After the sequence of a full system calibration is

complete, additional offset or gain calibrations can be performed

individually to adjust the system zero reference point or the

system gain. Calibrating one of the parameters, either system

offset or system gain, does not affect the other parameter.

When the part is used in unbuffered mode, system calibration

can be used to remove errors from source impedances on the

analog input. A simple R-C antialiasing filter on the front end

can introduce a gain error on the analog input voltage, but the

system calibration can be used to remove this error.

Span and Offset Limits

Whenever the system calibration mode is used, there are limits

on the amount of offset and span that can be accommodated.

The overriding requirement for determining the amount of

offset and gain that can be accommodated by the part is that the

positive full-scale calibration limit is < 1.05 × VREF/gain. This

allows the input range to go 5% above the nominal range. The

built-in headroom in the AD7705/AD7706 analog modulator

ensures that the parts operate correctly with a positive full-scale

voltage that is 5% beyond the nominal.

The range of input span in both the unipolar and bipolar modes

has a minimum value of 0.8 × VREF/gain and a maximum value of

2.1 × VREF/gain. However, when determining the span, which is

the difference between the bottom and top of the devices’ input

range, the user must take into account the limitation on the

positive full-scale voltage. The amount of offset that can be

accommodated depends on whether the unipolar or bipolar

mode is used, and the user must also take into account the

limitation on the positive full-scale voltage. In unipolar mode,

there is considerable flexibility in handling negative offsets with

respect to AIN(−) on the AD7705, and with respect to

COMMON on the AD7706. In both unipolar and bipolar

modes, the range of positive offsets that can be handled by the

part depends on the selected span. Therefore, in determining

the limits for system zero-scale and full-scale calibrations, the

user must ensure that the offset range plus the span range does

not exceed 1.05 × VREF/gain.

If the part is used in unipolar mode with a required span of

0.8 × VREF/gain, the offset range that the system calibration can

handle is –1.05 × VREF/gain to +0.25 × VREF/gain. If

the part is used in unipolar mode with a required span of

VREF/gain, the offset range that the system calibration can

handle is −1.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if

the part is used in unipolar mode and required to remove an

offset of 0.2 × VREF/gain, the maximum span range that the

system calibration can handle is 0.85 × VREF/gain.

EVAL-AD7705EB Datasheet(PDF) 26 Page - Analog Devices

EVAL-AD7705EB Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL